A Vertex Trigger based on Cylindrical Multiwire Proportional Chambers

TL;DR

The paper presents the CIP2k z-vertex trigger for the H1 detector at HERA II, built around a five-layer cylindrical MWPC with 8,480 readout pads to reconstruct vertex positions along the beam axis in real time. A pipelined FPGA-based trigger algorithm identifies tracks, assembles a z-vertex histogram across 22 bins, and makes a rapid decision to reject backward/background-heavy events while preserving ep events, all within a latency of about $1.5\ \mathrm{\mu s}$. The system achieves high spatial and time resolution, near-100% single-track efficiency for ep events, and demonstrably effective background suppression, including collimator-related backgrounds, thereby increasing H1 data-taking efficiency during the luminosity upgrade. The CIP2k architecture integrates with the existing trigger and DAQ infrastructure via optical links, I2C control, and VME-based data transfer, reflecting a robust, scalable approach to fast vertex-triggering in a high-rate environment.

Abstract

The article describes the technical implementation and the performance of the z-vertex trigger (CIP2k), which is part of the H1-experiment at HERA.

Figures (16)

• Figure 1: Synchrotron radiation background: Bending of the electrons (1) leads to a high amount of synchrotron radiation which reduces the quality of the vacuum in the beam pipe (2). As a consequence the background rate rises due to collisions of protons with rest gas nuclei (3), which are observed in the H1 detector as hadronic showers (4)
• Figure 2: Cross section of the five layer cylindrical multiwire proportional chamber with cathode pad readout.
• Figure 3: Side view of one layer of the CIP2k chamber in the $rz$-plane.
• Figure 4: Two HV supplies caen with trip protection are connected to 15 HV wires of the chamber covering 11.25$^\circ$ in $\varphi$.
• Figure 5: Block diagram of the CIPix PCB for one of the 64 channels.