A Fast High Resolution Track Trigger for the H1 Experiment

TL;DR

The paper presents the Fast Track Trigger (FTT) designed for the H1 experiment to cope with the HERA luminosity upgrade by delivering fast, high-resolution track information from L1 through L3. It describes a multi-tier hardware architecture where L1 performs coarse hit/segment finding with FPGA/CAMs, L2 conducts 2D linking and 3D fitting on DSP-based boards, and L3 uses a CPU farm to search for resonances and invariant masses. Simulated performance confirms adherence to the trigger timing constraints and demonstrates track resolutions close to offline quality, with D* resonance triggers achieving high efficiency. This architecture significantly enhances selective triggering for low-pT, track-based final states, enabling robust heavy-flavor and resonance studies in a high-rate environment.

Abstract

After 2001 the upgraded ep collider HERA will provide an about five times higher luminosity for the two experiments H1 and ZEUS. In order to cope with the expected higher event rates the H1 collaboration is building a track based trigger system, the Fast Track Trigger (FTT). It will be integrated in the first three levels (L1-L3) of the H1 trigger scheme to provide higher selectivity for events with charged particles. The FTT will allow to reconstruct 3-dimensional tracks in the central drift chamber down to 100 MeV/c within the L2 latency of ~ 23 mus. To reach the necessary momentum resolution of ~ 5% (at 1 GeV/c) sophisticated reconstruction algorithms have to be implemented using high density Field Programmable Gate Arrays (FPGA) and their embedded Content Addressable Memories (CAM). The final track parameter optimization will be done using non-iterative fits implemented in DSPs. While at the first trigger level rough track information will be provided, at L2 tracks with high resolution are available to form trigger decisions on topological and other track based criteria like multiplicities and momenta. At the third trigger level a farm of commercial processor boards will be used to compute physics quantities such as invariant masses.

Figures (6)

• Figure 1: $r-\phi$ view of a charged particle track from the interaction point traversing the central drift chamber of the H1 experiment. In addition to the boundaries of the chambers the sense and cathode wires are indicated. The four trigger layers formed out of three layers of wires each are marked by the thick dashed lines.
• Figure 2: The hardware realization of the FTT. After signal digitization and hit recognition the track segment finding is done on the Front End Modules (FEM). Via LVDS links and intermediate Merger Cards the track segments are first fed to the L1 Linker Card to generate a level 1 trigger decision and after a refined track segment finding sent to the L2 Linker Card, where full tracks are extracted followed by a 3-dimensional fitting on a Fitter Card. A Decision Card calculates second level trigger signals and serves as a link to the third level trigger where invariant mass sums are calculated on CPU boards. Each CPU board is used for a specific physics channel.
• Figure 3: Hits of one cell in a trigger layer are fed into shift registers schematically shown in this picture. The shift register information is used to find track segments which are basically characterized by straight lines as indicated by the dashed arrow.
• Figure 4: Schematic principle of the track linking step. The level 1 track segment information (marked as dots) is filled into a $\kappa$-$\phi$ histogram. Tracks successfully linked by the FTT are marked as circles while the boxes represent tracks found by the full H1 chamber reconstruction. The inset shows the principle of the 3 $\times$ 3 sliding window technique.
• Figure 5: Track resolution of the simulated FTT algorithm in $1/p_t$ and $\phi$ relative to the full off-line CJC reconstruction. The tracks studied are taken from a sample of $D^* \rightarrow K \pi \pi_{slow}$ candidates. Gaussian fits are shown to both distributions.