GPIR: Enabling Practical Private Information Retrieval with GPUs

Abstract

Private information retrieval (PIR) allows private database queries but is hindered by intense server-side computation and memory traffic. Modern lattice-based PIR protocols typically involve three phases: ExpandQuery (expanding a query into encrypted indices), RowSel (encrypted row selection), and ColTor (recursive "column tournament" for final selection). ExpandQuery and ColTor primarily perform number-theoretic transforms (NTTs), whereas RowSel reduces to large-scale independent matrix-matrix multiplications (GEMMs). GPUs are theoretically ideal for these tasks, provided multi-client batching is used to achieve high throughput. However, batching fundamentally reshapes performance bottlenecks; while it amortizes database access costs, it expands working sets beyond the L2 cache capacity, causing divergent memory behaviors and excessive DRAM traffic. We present GPIR, a GPU-accelerated PIR system that rethinks kernel design, data layout, and execution scheduling. We introduce a stage-aware hybrid execution model that dynamically switches between operation-level kernels, which execute each primitive operation separately, and stage-level kernels, which fuse all operations within a protocol stage into a single kernel to maximize on-chip data reuse. For RowSel, we identify a performance gap caused by a structural mismatch between NTT-driven data layouts and tiled GEMM access patterns, which is exacerbated by multi-client batching. We resolve this through a transposed-layout GEMM design and fine-grained pipelining. Finally, we extend GPIR to multi-GPU systems, scaling both query throughput and database capacity with negligible communication overhead. GPIR achieves up to 305.7x higher throughput than PIRonGPU, the state-of-the-art GPU implementation.

Figures (12)

• Figure 1: OnionPIRv2 computation process.
• Figure 2: Four job partitioning strategies for PIR operations. Each cuboid represents a BFV $\mathtt{ct}$ with two polynomials, each having four limbs (rows) and $N$ coefficients (columns).
• Figure 3: Roofline analysis of each PIR phase on an RTX 5090 with a 2GB $\mathtt{DB}$. Computational throughput is measured in terms of 32-bit integer multiply-and-add (IMAD) throughput.
• Figure 4: Operation-wise working set variation across ExpandQuery and ColTor phases under different batch sizes.
• Figure 5: Stage-wise DRAM transactions and execution time of operation-level and stage-level kernels under different batch sizes. (a, b) DRAM transactions per batch per node for ExpandQuery and ColTor. (c,d) Execution time per batch for ExpandQuery and ColTor.