LOCALUT: Harnessing Capacity-Computation Tradeoffs for LUT-Based Inference in DRAM-PIM

Abstract

Lookup tables (LUTs) have recently gained attention as an alternative compute mechanism that maps input operands to precomputed results, eliminating the need for arithmetic logic. LUTs not only reduce logic complexity, but also naturally support diverse numerical precisions without requiring separate circuits for each bitwidth-an increasingly important feature in quantized DNNs. This creates a favorable tradeoff in PIM: memory capacity can be used in place of logic to increase computational throughput, aligning well with DRAM-PIM architectures that offer high bandwidth and easily available memory but limited logic density. In this work, we explore this capacity-computation tradeoff in LUT-based PIM designs, where memory capacity is traded for performance by packing multiple MAC operations into a single LUT lookup. Building on this insight, we propose LOCALUT, a PIM-based design for efficient low-bit quantized DNN inference using operation-packed LUTs. First, we observe that these LUTs contain extensive redundancy and introduce LUT canonicalization, which eliminates duplicate entries to reduce LUT size. Second, we propose reordering LUT, a lightweight auxiliary LUT that remaps weight vectors to their canonical form required by LUT canonicalization with a simple LUT lookup. Third, we propose LUT slice streaming, a novel execution strategy that exploits the DRAM-buffer hierarchy by streaming only relevant LUT columns into the buffer and reusing them across multiple weight vectors. Evaluated on a real system based on UPMEM devices, we demonstrate a geometric mean speedup of 1.82x across various numeric precisions and DNN models. We believe LOCALUT opens a path toward scalable, low-logic PIM designs tailored for LUT-based DNN inference. Our implementation of LOCALUT is available at https://github.com/AIS-SNU/LoCaLUT.

Figures (21)

• Figure 1: DRAM-PIM architecture abstraction. Conventionally, bank-level PIM architectures involve local buffers and processing units near each DRAM bank.
• Figure 2: Operation-packed LUT with packing degree $p=3$.
• Figure 3: Baseline LUT-based approaches to perform matrix multiplications in DRAM-PIM. (a) Placing LUTs in DRAM. (b) Placing LUTs in the SRAM buffer. (c) Comparison results of the baseline approaches.
• Figure 4: LUT Canonicalization with the execution flow within a PIM architecture. (a) LUT canonicalization eliminates the redundant entries included in an operation-packed LUT. (b) To access the canonical LUT, the weight needs to be reordered.
• Figure 5: Illustration of Reordering LUT design. (a) Index reordering is replaced with a single reordering LUT lookup. (b) Execution flow with reordering LUT and canonical LUT while processing GEMM.