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DHFP-PE: Dual-Precision Hybrid Floating Point Processing Element for AI Acceleration

Shubham Kumar, Vijay Pratap Sharma, Vaibhav Neema, Santosh Kumar Vishvakarma

Abstract

The rapid adoption of low-precision arithmetic in artificial intelligence and edge computing has created a strong demand for energy-efficient and flexible floating-point multiply-accumulate (MAC) units. This paper presents a fully pipelined dual-precision floating-point MAC processing engine supporting FP8 formats (E4M3, E5M2) and FP4 formats (E2M1, E1M2), specifically optimized for low-power and high-throughput AI workloads. The proposed architecture employs a novel bit-partitioning technique that enables a single 4-bit unit multiplier to operate either as a standard 4x4 multiplier for FP8 or as two parallel 2x2 multipliers for 2-bit operands, achieving 100 percent hardware utilization without duplicating logic. Implemented in 28 nm technology, the proposed processing engine achieves an operating frequency of 1.94 GHz with an area of 0.00396 mm^2 and power consumption of 2.13 mW, resulting in up to 60.4 percent area reduction and 86.6 percent power savings compared to state-of-the-art designs.

DHFP-PE: Dual-Precision Hybrid Floating Point Processing Element for AI Acceleration

Abstract

The rapid adoption of low-precision arithmetic in artificial intelligence and edge computing has created a strong demand for energy-efficient and flexible floating-point multiply-accumulate (MAC) units. This paper presents a fully pipelined dual-precision floating-point MAC processing engine supporting FP8 formats (E4M3, E5M2) and FP4 formats (E2M1, E1M2), specifically optimized for low-power and high-throughput AI workloads. The proposed architecture employs a novel bit-partitioning technique that enables a single 4-bit unit multiplier to operate either as a standard 4x4 multiplier for FP8 or as two parallel 2x2 multipliers for 2-bit operands, achieving 100 percent hardware utilization without duplicating logic. Implemented in 28 nm technology, the proposed processing engine achieves an operating frequency of 1.94 GHz with an area of 0.00396 mm^2 and power consumption of 2.13 mW, resulting in up to 60.4 percent area reduction and 86.6 percent power savings compared to state-of-the-art designs.

Paper Structure

This paper contains 12 sections, 5 figures, 2 tables.

Table of Contents

  1. Introduction
  2. Theoretical Analysis
  3. Floating Point MAC Operation
  4. Bit Partitioning
  5. Implementation of variable precision MAC
  6. Proposed Architecture
  7. Architecture of a 6-stage pipeline
  8. Experiment Results
  9. Performance Evolution
  10. Performance Comparison at stage
  11. FPGA Implementation
  12. Conclusion and Future Work

Figures (5)

  • Figure 1: Supported FP formats of the proposed Processing Element.
  • Figure 2: Supported FP formats of the proposed Processing Element.
  • Figure 3: Supported FP formats of the proposed Processing Element across different process corners.
  • Figure 4: Datapath of the proposed fully-pipelined dual-precision PE.
  • Figure 5: Supported FP formats of the proposed Processing Element.