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Area Optimization of Open-Source Low-Power INA in 130nm CMOS using Hybrid Mixed-Variable PSO

Avishka Herath, Chanula Luckshan, Lochana Katugaha, Udara Mendis, Kithmin Wickremasinghe

Abstract

As open-source silicon initiatives democratize access to integrated circuit development using multi-project environments, silicon area has become a premium resource. However, minimizing this layout area traditionally forces designers to compromise on core performance specifications. To address this challenge, this paper presents an open-source framework based on a hybrid mixed-variable particle swarm optimization algorithm and the gm/ID methodology to minimize the layout area of complex analog circuits while meeting design requirements. The framework's efficacy is demonstrated by designing a low-power instrumentation amplifier that achieves a 90.33% reduction in gate area over existing implementations.

Area Optimization of Open-Source Low-Power INA in 130nm CMOS using Hybrid Mixed-Variable PSO

Abstract

As open-source silicon initiatives democratize access to integrated circuit development using multi-project environments, silicon area has become a premium resource. However, minimizing this layout area traditionally forces designers to compromise on core performance specifications. To address this challenge, this paper presents an open-source framework based on a hybrid mixed-variable particle swarm optimization algorithm and the gm/ID methodology to minimize the layout area of complex analog circuits while meeting design requirements. The framework's efficacy is demonstrated by designing a low-power instrumentation amplifier that achieves a 90.33% reduction in gate area over existing implementations.

Paper Structure

This paper contains 20 sections, 7 equations, 5 figures, 2 tables.

Table of Contents

  1. Introduction
  2. Optimization Problem Overview
  3. gm/ID Primer using SKY130A Process Design Kit (PDK)
  4. Problem Formulation
  5. Design Variables, Objective Function, and Constraints
  6. Optimization Methodology
  7. Particle Generation
  8. Initial Bound Selection
  9. Dynamic Bound Adjustment
  10. Survivability Test (PyGMID)
  11. Verification Test (PySpice)
  12. Particle Swarm Optimization for Mixed-Variable Problems
  13. Continuous Reproduction Method
  14. Discrete Reproduction Method
  15. Adaptive Parameter Selection
  16. ...and 5 more sections

Figures (5)

  • Figure 1: Schematic of an FDDA-based INA at the transistor level.
  • Figure 2: Overview of the proposed HMV-PSO optimization framework for layout area minimization. Given design specifications, LUT data, PDK models, and a parameterizable SPICE netlist as inputs, the flow proceeds through: (A) particle generation within adaptively bounded search spaces; (B) analytical feasibility filtering via PyGMID; (C) full-circuit SPICE verification via PySpice; and (D) iterative PSO-based position updates cycling through (A)–(C) until convergence on the area-optimal sizing. (E) The resulting solution is used for the standard physical design flow to produce the GDSII layout.
  • Figure 3: HMV-PSO convergence over 60 iterations: (top) layout area reduction across 5 runs; (bottom) $g_m/I_{D,i}$ trajectories and inversion levels for Run 3.
  • Figure 4: Layout of the FDDA and CMFB circuit ($80.12\ \mu$m $\times$$25.26\ \mu$m).
  • Figure 5: Post-layout simulation results of the FDDA circuit: frequency response plot showing the gain, phase, CMRR, and PSRR after parasitic extraction.