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Negative-Voltage-Enabled Energy Efficient Nonvolatile Memories And In-Memory Computing Based On 2D Piezoelectric Transistors

Jeffry Victor, Sumeet K. Gupta

Abstract

Piezoelectric FET (PeFET) is a promising non-volatile-memory (NVM) device that integrates a piezoelectric (PE)/ferroelectric (FE) capacitor with a 2D transistor. It uses the polarization of the FE capacitor for bit-storage and strain-induced bandgap change of the 2D channel during read. Previous PeFET-based NVM designs have shown immense promise in achieving high density and energy-efficiency compared to SRAM. However, a key limitation of these designs is that they must trade-off integration density to enhance energy-efficiency or augment the memory functionality with in-memory computing (IMC). In this work, we show that the unique structure of the PeFET presents an appealing opportunity to counter these limitations, thereby simultaneously achieving high density, high energy-efficiency, and IMC-compatibility. First, we highlight the key reasons for the limited energy-efficiency of the previous PeFET designs. Based on these insights, we propose two flavors of PeFET memories that utilize negative voltage (NeVo) to reduce the major energy-consuming components significantly. Compared to 6T-SRAM (prior PeFET-based NVMs), the proposed designs achieve substantial reductions in energy, lowering read energy to 0.08x(0.03x) and write energy to 0.19x(0.53x), respectively. We then leverage these cells to implement IMC primitives, such as addition, subtraction, and multiply-and-accumulate (MAC), achieving 0.03x the energy consumption of prior PeFET-based designs.

Negative-Voltage-Enabled Energy Efficient Nonvolatile Memories And In-Memory Computing Based On 2D Piezoelectric Transistors

Abstract

Piezoelectric FET (PeFET) is a promising non-volatile-memory (NVM) device that integrates a piezoelectric (PE)/ferroelectric (FE) capacitor with a 2D transistor. It uses the polarization of the FE capacitor for bit-storage and strain-induced bandgap change of the 2D channel during read. Previous PeFET-based NVM designs have shown immense promise in achieving high density and energy-efficiency compared to SRAM. However, a key limitation of these designs is that they must trade-off integration density to enhance energy-efficiency or augment the memory functionality with in-memory computing (IMC). In this work, we show that the unique structure of the PeFET presents an appealing opportunity to counter these limitations, thereby simultaneously achieving high density, high energy-efficiency, and IMC-compatibility. First, we highlight the key reasons for the limited energy-efficiency of the previous PeFET designs. Based on these insights, we propose two flavors of PeFET memories that utilize negative voltage (NeVo) to reduce the major energy-consuming components significantly. Compared to 6T-SRAM (prior PeFET-based NVMs), the proposed designs achieve substantial reductions in energy, lowering read energy to 0.08x(0.03x) and write energy to 0.19x(0.53x), respectively. We then leverage these cells to implement IMC primitives, such as addition, subtraction, and multiply-and-accumulate (MAC), achieving 0.03x the energy consumption of prior PeFET-based designs.

Paper Structure

This paper contains 30 sections, 18 figures, 2 tables.

Table of Contents

  1. Introduction
  2. Background
  3. PeFET structure and operation
  4. PeFET based NVMs
  5. Energy Analysis of PeFET NVMs
  6. Generation of negative voltage
  7. NeVo HD PeFET NVM
  8. NeVo HD PeFET Bit-cell and Array
  9. Read Operation based on Current Sensing
  10. Read Operation based on Voltage Sensing
  11. Write Operation in NeVo HD
  12. NeVo 2T-1P PeFET NVM
  13. Read based on Current Sensing
  14. Read based on Voltage Sensing in NeVo 2T-1P
  15. Write Operation in NeVo 2T-1P
  16. ...and 15 more sections

Figures (18)

  • Figure 1: (a) PeFET device (b) PeFET schematic (c) Strain vs $V_{GB}$ for +ve $V_{GB}$ (d) IV characteristics for +ve $V_{GB}$
  • Figure 2: Schematic and layouts of (a) HD (b) 1T-1P (c) CC and (d) 2T-1P NVMs.
  • Figure 3: Segmented Memory Array
  • Figure 4: Analyzing the contribution of different components in current-sensing read energy of HD and 2T-1P normalized to each NVM
  • Figure 5: NeVo HD (a) Schematic (b) Array and (c) Layout
  • ...and 13 more figures