EEspice: A Modular Circuit Simulation Platform with Parallel Device Model Evaluation via Graph Coloring

Abstract

As modern analogue/mixed-signal design increasingly relies on optimization-in-the-loop flows, such as AI and LLM-based sizing agents that repeatedly invoke SPICE-efficient, accurate high-performance simulators have become an indispensable foundation for modern integrated circuit (IC) design. However, the computational cost of evaluating nonlinear models, particularly for BSIM models, remains a significant bottleneck. In standard parallelization approaches, devices such as transistors are easily distributed across processors. The subsequent stamping phase, where each device's contributions are added to the shared system matrix, often creates a bottleneck. Because multiple processor cores compete to update the same matrix elements simultaneously, the system is forced to process tasks one at a time to avoid errors. This paper introduces EEspice, an open-source circuit simulation framework whose modular architecture decouples device model evaluation into independently replaceable kernels, enabling a parallel stamping strategy that overcomes this bottleneck. It partitions MOSFET instances into independent color groups, which can be processed in parallel. Our results show that on a 64-core workstation, the proposed approach achieves up to 45x speedup over single-thread performance when conflicts are low. Our analysis also explores how performance depends on circuit topology.

Figures (7)

• Figure 1: Typical transient simulation flowchart.
• Figure 2: Accuracy comparison versus Ngspice: (a) BSIM4 FET DC $I$--$V$ characteristics overlaid for multiple $V_{GS}$ values, and (b)Inverter transient waveforms ($V(in)$ and $V(out)$) overlaid.
• Figure 3: Example of mapping of a 5-transistor Operational Transconductance Amplifier (5T OTA) with a current mirror to a conflict graph for parallel matrix stamping. Each MOSFET instance, such as M1 and M2, is represented as a graph vertex. An edge connects devices that share a common non-ground circuit node, indicating a potential write conflict during stamping. The assigned colors illustrate the partitioning of these devices into independent, conflict-free sets that can be evaluated and stamped concurrently without atomic locks.
• Figure 4: A typical 28T CMOS full adder circuit.
• Figure 5: BSIM4 evaluation time breakdown for thread count $N=1000$ under moderate conflict when the number of colors is $C=26$. (a) loadomp showing computation time $t_{calc}$ in blue, scaling while stamping time $t_{stamp}$ in orange, remains a serial bottleneck (b) Color showing parallelized stamping within color groups, which reduces the total iteration time and prevents the serial bottleneck effect.