The Darkside-20k Data Acquisition System

Abstract

DarkSide-20k is a WIMP search experiment using liquid argon as a target, designed to perform a background-free search for dark matter with unprecedented sensitivity, and is currently under construction at INFN Laboratori Nazionali del Gran Sasso, Italy. The detector comprises a dual-phase Time Projection Chamber complemented with external veto systems and is equipped with a total of 2720 SiPM-based readout channels. This work presents the DAQ system designed for DarkSide-20k. The system is capable of continuous, triggerless digitisation of the waveforms with high single-photoelectron detection efficiency and online processing, ensuring data reduction for long-term storage. The DarkSide-20k DAQ system employs commercial CAEN VX2745 digitisers with custom FPGA firmware implementation. Timing and synchronisation across all 48 digitisers are provided by custom Global and Crate Data Manager boards distributing a phase-aligned clock derived from a disciplined rubidium standard. Waveform segments are processed in real time by Front End Processor machines. Data are organised into collections containing whole detector information and distributed across a farm of Time Slice Processors for event reconstruction, classification, and further reduction before storage and offline analysis. A full "Quadrant" of the system, corresponding to one quarter of the final DAQ, has been assembled and validated at TRIUMF laboratory in Canada. The Quadrant has been stress-tested with simultaneous pulses and demonstrated sustained digitizer readout exceeding expected physics rates and stable long-term performance.

Figures (12)

• Figure 1: Cross-sectional view of the detector. The is equipped with top and bottom Optical Planes (1). At the top of the (2), a thin layer of gaseous argon together with a stainless-steel grid enables the production of the electroluminescence signal. The is enclosed in the Inner and Outer Vetos (IV and OV).
• Figure 2: Schematic representation of the network. At the lower part of the diagram, the ($1$) and the ($2$) are interconnected to distribute the clock and commands to the waveform digitisers (, for vetos and , 3 and 4 respectively). Each digitiser is connected through a network switch ($5$) to dedicated computers ($6$), where digitised waveforms are processed with a matched filter, and a peak finder is applied to identify hits within the waveform. Optical network cables connect the network switches to the , which, in turn, are connected to a network data switch ($7$). These connections are implemented using individual optical links operating at 10GbE. The Pool Manager ($8$) distributes the detector data to a cluster of ($9$), where online reconstruction is performed. Data from multiple are collected by the Merger machine ($10$) and stored on a local disk. The data traffic between the digitisers and the is managed by the server ($8$) acting as an interface to all components, integrating communication and hardware configuration (, , CDMs) and ($11$). This includes the management of ($11$), VME crates, and power supplies through a network switch ($12$). Finally, the data are transferred for external storage through the Gateway machine ($13$) connected to the network.
• Figure 3: concept: the acquisition timeline is segmented into 1s intervals, each directed to a dedicated for further analysis. Since lacks access to previously processed slices, a portion of each (5m s) is duplicated and sent to the next . Time Slice Markers (TSMs) ensure proper segment assembly (see \ref{['sec:gdm_cdm']}).
• Figure 4: Schematic representation of the data path within the VX2745 boards. The Sort & Merge buffer collects data from all the channels (CH) with a speed of 64bit at 4n s, $250MHz$. Since each 64-bit word contains four 16-bit ADC samples, this corresponds to an effective throughput of 1000 MS/s, i.e. eight times the ADC sampling rate of 125 MS/s. Waveform segments are then transferred to a 2G DDR4 memory with a speed of 640b over about 10 clocks of 200M Hz then to an ARM CPU and finally to the .
• Figure 5: Schematic representation of the busy logic within a digitiser module. Black lines represent the data readout, while the orange line represents the data transmission. Segment start and end times are identified by black and red arrows, respectively.