Escaping Flatland: A Placement Flow for Enabling 3D FPGAs

Abstract

3D field-programmable gate arrays (FPGAs) promise higher performance through vertical integration. However, existing placement tools, largely inherited from 2D frameworks, fail to capture the unique delay characteristics and optimization dynamics of 3D fabrics. We introduce a 3D FPGA placement flow that integrates partitioning-based initialization, adaptive cost scheduling, refined delay estimation, and a simulated annealing move set -- all targeted at 3D FPGA architecture. Together, these enhancements improve timing estimates and the exploration of layer assignments during placement. Compared to Verilog-To-Routing (VTR), our experiments show geometric-mean (max) critical-path delay reductions of ~3% (~7%), ~2% (~4%), ~3% (~8%), and ~6% (~18%) for four 3D architectures: 3D CB, 3D CB-O, 3D CB-I, and 3D SB, respectively. We also achieve geometric-mean (max) routed wirelength reductions of ~1% (~3%), ~2% (~8%), < 1% (~5%), and ~5% (~10%), respectively. Our work will be permissively open-sourced on GitHub.

Figures (7)

• Figure 1: Overview of our 3D FPGA placement flow.
• Figure 2: 3D FPGA architectures based on connection types. Connections are only shown from layer "L2" to layer "L1". Green arrows show hybrid variations of each architecture.
• Figure 3: Pareto fronts across the four architectures. CPD and WL are normalized to 3D-baseline. Stars = chosen configs.
• Figure 4: Ablation studies on a subset of the Koios benchmarks.
• Figure 5: Runtime profiling on 3D CB. Results are normalized to 3D-baseline and averaged over 10 seeds.