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Geometry-induced correlated noise in qLDPC syndrome extraction

Angelo Di Bella

Abstract

With code and syndrome-extraction schedule fixed, can routed geometry alone change the correlated fault model enough to impact logical performance? Starting from a geometry-conditioned same-tick interaction Hamiltonian, we derive a controlled retained single-and-pair data-fault model for bivariate-bicycle (BB) layouts. Two geometry metrics emerge in two kernel regimes: under a crossing-local diagnostic kernel, a matching argument reduces the support-level effective fault weight; when every support pair appears in at least one retained round with finite same-round separation, strictly positive kernels saturate the support graph, and weighted exposure becomes the discriminating quantity. Circuit-level Monte Carlo on the $[\![72, 12, 6]\!]$ and $[\![144, 12, 12]\!]$ benchmarks confirms that a biplanar bounded-thickness layout suppresses the monomial single-layer embedding penalty, with weighted exposure tracking logical error rate across 101 operating points (Spearman correlation 0.893). A single-layer logical-family optimization on BB72 reduces worst-case exposure by 26.11% and lowers logical error rate in the tested power-law window. Routed geometry should be optimized together with code, schedule, and decoder.

Geometry-induced correlated noise in qLDPC syndrome extraction

Abstract

With code and syndrome-extraction schedule fixed, can routed geometry alone change the correlated fault model enough to impact logical performance? Starting from a geometry-conditioned same-tick interaction Hamiltonian, we derive a controlled retained single-and-pair data-fault model for bivariate-bicycle (BB) layouts. Two geometry metrics emerge in two kernel regimes: under a crossing-local diagnostic kernel, a matching argument reduces the support-level effective fault weight; when every support pair appears in at least one retained round with finite same-round separation, strictly positive kernels saturate the support graph, and weighted exposure becomes the discriminating quantity. Circuit-level Monte Carlo on the and benchmarks confirms that a biplanar bounded-thickness layout suppresses the monomial single-layer embedding penalty, with weighted exposure tracking logical error rate across 101 operating points (Spearman correlation 0.893). A single-layer logical-family optimization on BB72 reduces worst-case exposure by 26.11% and lowers logical error rate in the tested power-law window. Routed geometry should be optimized together with code, schedule, and decoder.

Paper Structure

This paper contains 47 sections, 20 theorems, 73 equations, 18 figures, 4 tables, 1 algorithm.

Table of Contents

  1. Introduction
  2. Microscopic model and retained effective channel
  3. Open system and routed geometry
  4. Pauli twirl and two-block corollary
  5. Crossing kernel and routed geometry
  6. Retained sector model and embedding families
  7. Circuit-level noise placement
  8. Effective distance, weighted exposure, and the AKP-type compatibility
  9. Adversarial effective-distance reduction
  10. Support saturation and weighted exposure for positive kernels
  11. Worked BB72 support and crossing-local reduction
  12. Weighted exposure under positive kernels
  13. Two-dimensional summability and the AKP-type compatibility
  14. Logical-aware single-layer design program
  15. BB72 family
  16. ...and 32 more sections

Key Result

Proposition 1

Let $\mathcal{H}_e$ and $\mathcal{H}_{e'}$ be the Hilbert spaces of two disjoint active gate blocks with dimensions $D_e$ and $D_{e'}$, and let $\hat{K}$ be any Hermitian operator on $\mathcal{H}_e\otimes\mathcal{H}_{e'}$. Then there exists a unique decomposition where $c\in\mathbb{R}$, the local operators $\hat{A}_e$ and $\hat{B}_{e'}$ are traceless Hermitian on their respective blocks, and $\ha

Figures (18)

  • Figure 1: Geometry-to-noise-to-performance pipeline. The left block contrasts the single-layer monomial embedding with the biplanar bounded-thickness construction; the central boxes track the microscopic Hamiltonian, twirl, retained sector model, and support-level graph objects; the rightmost box records the circuit-level logical performance tested on BB72 and BB144. The two analytical branches beneath the support-level box distinguish the crossing-local diagnostic ($\kappa_{\times}$) from the strictly-positive-kernel regime ($\kappa>0$).
  • Figure 2: Theorem-level and implemented bounded-thickness embeddings. (a) The schematic thickness-two cartoon: all qubit sites lie in the base plane $\Pi_0$ (shown as the toric register grid), while the relevant same-round route families $G_A$ and $G_B$ are assigned to distinct routing slabs $\Pi_+$ and $\Pi_-$; dotted lines indicate layer access and smooth curves show schematic non-crossing in-plane routes. No same-layer crossing is shown or required. (b) The biplanar bounded-thickness realization used in the numerical study. Solid lines show representative in-plane traverses; dotted lines show the layer access paths connecting $\Pi_0$ to the routing slabs. The two blue traverses in $\Pi_+$ ($B_3$ and $A_2$, both in $G_A$) connect qubits at different toric-grid depths, so they project to different positions within the slab. The inter-layer separation $2h$ prevents same-round crossings across $G_A$ and $G_B$. This panel visualizes the realized bounded-thickness routing; it does not reconstruct the hardware geometry of Ref. bravyi_memory_2024.
  • Figure 3: Worked BB72 bridge from routed crossings to the support graph. Panel (a) shows the $B_3$-round crossing picture on the BB72 reference support $S_{\mathrm{ref}}$ in the four-column monomial embedding. Each same-round blue-red crossing pair induces an edge of the support graph. Panel (b) shows the resulting support graph after collecting those $B_3$ contributions and then adding the $\Delta_B$ triangle generated by rounds $B_1$ and $B_2$ on the $B$ side. The highlighted matching has size $\nu_{\phi}^{X}(L_{\mathrm{ref}})=3$, giving the support-level bound $d_{\mathrm{eff},X}(\phi)\le 6-3=3$.
  • Figure 4: BB72 crossing-kernel diagnostic sweep in the $X$ sector at physical depolarizing rate $p=10^{-3}$ and 6 cycles. The monomial embedding shows a rapid increase in logical error rate with coupling strength, whereas the biplanar bounded-thickness embedding remains at or near the sampling floor throughout the explored window. Error bars are 95% confidence intervals; open markers denote zero-failure operating points, plotted at the 95% upper bound. The crossing kernel isolates only the combinatorial crossing mechanism.
  • Figure 5: Main BB72 distance-decay results in the $X$ sector. (a) Power-law coupling sweep at fixed $\alpha=3$ and $p=10^{-3}$. The logical-aware single-layer points are shown at the four couplings available in the present processed dataset, $J_0\tau\in\{0.02,0.03,0.04,0.06\}$. (b) Power-law exponent sweep at fixed $J_0\tau=0.04$ and $p=10^{-3}$. The monomial and biplanar bounded-thickness embeddings are shown on the full exponent grid, while the logical-aware embedding is shown on the available mini-slice $\alpha\in\{2,3,5\}$. Across the explored regime, the biplanar bounded-thickness embedding suppresses the geometry-induced logical penalty relative to the monomial single-layer embedding, and the logical-aware embedding lies strictly between them on the tested points.
  • ...and 13 more figures

Theorems & Definitions (41)

  • Proposition 1: General two-block decomposition
  • proof
  • Corollary 1: First-order local-field reduction
  • proof
  • Remark 1
  • Theorem 1: General single-block Pauli twirl
  • proof
  • Corollary 2: Interaction two-block twirl
  • proof
  • Proposition 2: Controlled low-body truncation
  • ...and 31 more