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RePart: Efficient Hypergraph Partitioning with Logic Replication Optimization for Multi-FPGA System

Zizhuo Fu, Yifan Zhou, Zhaoxin Lu, Guangyu Sun, Runsheng Wang, Meng Li, Yibo Lin

Abstract

Multi-FPGA systems (MFS) are widely adopted for VLSI emulation and rapid prototyping. In an MFS, FPGAs connect only to a limited number of neighbors through bandwidth-constrained links, so inter-FPGA communication cost depends on network topology. This setting exposes two fundamental limitations of existing MFS-aware partitioning methods: conventional hypergraph partitioners focus solely on cut size and ignore topological structure, and they leave substantial FPGA resources unused due to conservative balance margins. We present RePart, a fully customized multilevel hypergraph partitioning framework for MFS that integrates logic replication with topology-aware optimization. RePart introduces three coordinated innovations across the multilevel pipeline: FPGA-aware dynamic coarsening, heat-value guided assignment, and replication-deletion supported refinement. Extensive experiments on the Titan23 and EDA Elite Challenge Contest benchmarks show that RePart reduces total hop distance by 52.3% on average over state-of-the-art hypergraph partitioners with an 11.1x speedup, and outperforms the EDA Elite Challenge winners. Code is available at: https://github.com/Welement-zyf/RePart.

RePart: Efficient Hypergraph Partitioning with Logic Replication Optimization for Multi-FPGA System

Abstract

Multi-FPGA systems (MFS) are widely adopted for VLSI emulation and rapid prototyping. In an MFS, FPGAs connect only to a limited number of neighbors through bandwidth-constrained links, so inter-FPGA communication cost depends on network topology. This setting exposes two fundamental limitations of existing MFS-aware partitioning methods: conventional hypergraph partitioners focus solely on cut size and ignore topological structure, and they leave substantial FPGA resources unused due to conservative balance margins. We present RePart, a fully customized multilevel hypergraph partitioning framework for MFS that integrates logic replication with topology-aware optimization. RePart introduces three coordinated innovations across the multilevel pipeline: FPGA-aware dynamic coarsening, heat-value guided assignment, and replication-deletion supported refinement. Extensive experiments on the Titan23 and EDA Elite Challenge Contest benchmarks show that RePart reduces total hop distance by 52.3% on average over state-of-the-art hypergraph partitioners with an 11.1x speedup, and outperforms the EDA Elite Challenge winners. Code is available at: https://github.com/Welement-zyf/RePart.

Paper Structure

This paper contains 26 sections, 9 equations, 5 figures, 5 tables.

Table of Contents

  1. Introduction
  2. Preliminary
  3. Multi-FPGA System and Modeling
  4. Multilevel Hypergraph Partitioning Framework
  5. Methodology
  6. Overview
  7. Dynamic Coarsening with FPGA-Aware Scoring
  8. Connectivity and Balance Scoring
  9. Adaptive Penalty Adjustment
  10. Heat-Value Guided Assignment
  11. Heat-Value Metrics
  12. Deep Backtracking Exploration
  13. Logic Replication and Deletion Supported Refinement
  14. Four-Operation Framework
  15. Multi-Operator Coordination via $1+3K$-Heap
  16. ...and 11 more sections

Figures (5)

  • Figure 1: (a) Interconnect topology of a multi-FPGA system with heterogeneous resource constraints. (b) Communication reduction through strategic logic replication.
  • Figure 2: Dynamic Coarsening Process.
  • Figure 3: Heat-Value Guided Assignment Process.
  • Figure 4: Logic Replication Supported Refinement Process.
  • Figure 5: Ablation study on the EDA Contest benchmark. Normalized total hop distance is shown for coarsening (top), assignment (middle), and refinement (bottom).