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Quantum Non-Moduler Multiplication with QFT-Based Multi Input Parallelized Adder

Murat Kurtand Selçuk Çakmak, Azmi Gençten

Abstract

In this study, we propose an efficient quantum multiplication approach based on a QFT-assisted parallelized addition scheme. The multiplication stage is implemented using a structure composed entirely of Toffoli gates, which generate partial products. In the second stage, these partial results are accumulated using a QFT-based adder. Unlike conventional QFT-based arithmetic circuits, the proposed design eliminates the repeated application of QFT and inverse QFT (IQFT) operations during intermediate summation processes. This leads to a significant reduction in the total gate count and circuit complexity, enabling a more resource-efficient implementation. To demonstrate the feasibility of the proposed approach, a quantum circuit that performs the multiplication of two 3-bit numbers is designed. The circuit is tested and validated using IBM quantum simulators. The results indicate that the proposed method provides a more efficient alternative to traditional quantum multiplication techniques in terms of gate cost and circuit depth.

Quantum Non-Moduler Multiplication with QFT-Based Multi Input Parallelized Adder

Abstract

In this study, we propose an efficient quantum multiplication approach based on a QFT-assisted parallelized addition scheme. The multiplication stage is implemented using a structure composed entirely of Toffoli gates, which generate partial products. In the second stage, these partial results are accumulated using a QFT-based adder. Unlike conventional QFT-based arithmetic circuits, the proposed design eliminates the repeated application of QFT and inverse QFT (IQFT) operations during intermediate summation processes. This leads to a significant reduction in the total gate count and circuit complexity, enabling a more resource-efficient implementation. To demonstrate the feasibility of the proposed approach, a quantum circuit that performs the multiplication of two 3-bit numbers is designed. The circuit is tested and validated using IBM quantum simulators. The results indicate that the proposed method provides a more efficient alternative to traditional quantum multiplication techniques in terms of gate cost and circuit depth.

Paper Structure

This paper contains 11 sections, 7 equations, 8 figures.

Table of Contents

  1. Introduction
  2. Theory
  3. Toffoli Gate
  4. Quantum Fourier Transform
  5. QFT-Based Parallelized Addition Circuit
  6. Elementary School Multiplication Method
  7. Results and Discussion
  8. Part of Multiplication
  9. Three bit number Example
  10. Conclusion
  11. ACKNOWLEDGMENTS

Figures (8)

  • Figure 1: Quantum Circuit Representation of the Toffoli Gate
  • Figure 2: Generalized QFT Circuit (For qubit systems d = 2)
  • Figure 3: QFT-Based Parallelized Addition Circuit
  • Figure 4: Elementary Multiplication Operation Diagram
  • Figure 5: Non-Modular Multiplication with QFT-Based Multi-Input Parallelized Adder Circuit ($\mathrm{n}$-bit $\mathrm{N}$-input)kurt2024
  • ...and 3 more figures