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A Security-Aware Nonlinearity Study of FPGA-Based Time-to-Digital Converters for Quantum Key Distribution Systems

Kun Qin, Carsten Trinitis

Abstract

Intrinsic nonlinearity in FPGA-based time-to-digital converters (TDCs) is often treated as a calibration issue and evaluated mainly through post-correction metrics. In quantum key distribution (QKD), however, raw delay-line nonuniformity can affect coincidence timing and thereby influence accidental-coincidence rate and Quantum Bit Error Rate (QBER). This paper analyzes how measured FPGA-TDC nonlinearity propagates to QKD timing metrics using a conservative system-level model that combines random timing uncertainty and deterministic nonlinearity. We also propose fabric-level mitigation strategies based on LUT-assisted delay shaping and placement constraints to reduce severe bin-width irregularities without statistical calibrations. The method is evaluated by reproducing two open-source TDCs implemented on a low-cost Zynq-7000 FPGA. We observe reductions of 14\%-21\% in integral nonlinearity (INL) compared with the non-optimized design, leading to a reduced QBER contribution and an improvement by 3.7\%-14.2\% in the estimated secret fraction. These results suggest that raw FPGA-TDC nonlinearity deserves explicit consideration in timing-sensitive QKD implementations.

A Security-Aware Nonlinearity Study of FPGA-Based Time-to-Digital Converters for Quantum Key Distribution Systems

Abstract

Intrinsic nonlinearity in FPGA-based time-to-digital converters (TDCs) is often treated as a calibration issue and evaluated mainly through post-correction metrics. In quantum key distribution (QKD), however, raw delay-line nonuniformity can affect coincidence timing and thereby influence accidental-coincidence rate and Quantum Bit Error Rate (QBER). This paper analyzes how measured FPGA-TDC nonlinearity propagates to QKD timing metrics using a conservative system-level model that combines random timing uncertainty and deterministic nonlinearity. We also propose fabric-level mitigation strategies based on LUT-assisted delay shaping and placement constraints to reduce severe bin-width irregularities without statistical calibrations. The method is evaluated by reproducing two open-source TDCs implemented on a low-cost Zynq-7000 FPGA. We observe reductions of 14\%-21\% in integral nonlinearity (INL) compared with the non-optimized design, leading to a reduced QBER contribution and an improvement by 3.7\%-14.2\% in the estimated secret fraction. These results suggest that raw FPGA-TDC nonlinearity deserves explicit consideration in timing-sensitive QKD implementations.

Paper Structure

This paper contains 17 sections, 8 equations, 5 figures, 2 tables.

Table of Contents

  1. Introduction
  2. Background and Motivation
  3. Nonlinearity of TDC and Calibration Methods
  4. Security-Aware Coincidence Timing in QKD
  5. Gap in QKD-Oriented Analysis of TDC Raw Nonlinearity
  6. Impact of TDC's Nonlinearity on QKD Metrics
  7. TDC's Impact of Random and Deterministic Nonlinearity
  8. TDC-Induced QBER Formulation
  9. Methodology and Proposed Strategies
  10. Two TDC Designs Under Test
  11. LUT-Based Delay Injection
  12. Placement-Constrained Delay-Line optimisation
  13. Results and Discussion
  14. Evaluation Setup
  15. Improved Nonlinearity
  16. ...and 2 more sections

Figures (5)

  • Figure 1: Typical structure of a tapped delay line and a CARRY4 primitive. (a) A tapped delay line is formed by a chain of delay elements with Flip-flops for sampling the signal. (b) CARRY4 (Zynq-7000 FPGA) is a dedicated, high-speed carry logic component used to implement fast arithmetic functions, bypassing general-purpose logic fabrics. Each stage, separated by a multiplexer, is used as a delay unit in the tapped delay line.
  • Figure 2: Raw bin-to-time transfer functions of TDC-1 and TDC-2. (a) Full delay-chain transfer functions. (b) Zoom-in: a severe local distortion in TDC-1, where an ultra-wide bin produces a step-like offset that propagates to subsequent codes.
  • Figure 3: Additional LUT-based inverters are added to the delay chain.
  • Figure 4: Example: Applying LOC constraints to DFFs.
  • Figure 5: Incremental QBER with TDC-1 and SPAD. We sweep the generated signal single rate of around 2 Mcps in our simulation because the observed actual single rate in the experiment was 1.59 Mcps b22.