Junction-Intrinsic Dissipation in Hybrid Superconductor-Semiconductor Gatemon Qubits

Abstract

Superconducting transmon qubits based on hybrid superconductor-semiconductor Josephson junctions (gatemons) offer gate tunability, but their relaxation times remain well below those of state-of-the-art transmons, and the origin of this discrepancy is not fully understood. Here, we co-fabricate gatemons and SIS-junction transmons with nominally identical circuit layouts, gate dielectrics, and control lines, so that the Josephson element is the only intentional distinction. Across multiple chips, transmons in this architecture reach relaxation times in the tens of microseconds, whereas gatemons saturate in the few-microsecond range. Using the transmons as on-chip references, we construct a loss budget including Purcell decay, spontaneous emission through the control line, and internal dielectric loss, and find that the corresponding T1 limits exceed all measured gatemon values by more than an order of magnitude. Temperature-dependent T1 measurements follow a common quasiparticle-activation model and yield similar superconducting gaps for S-Sm-S and SIS junctions, indicating that the reduced gatemon coherence is dominated by additional temperature-independent, junction-intrinsic dissipation.

Figures (8)

• Figure 1: (a) Optical image of the device containing both gatemon (left) and transmon (right) qubits. Meandered readout resonators are capacitively coupled to the qubit islands for dispersive readout. The transmons and gatemons share an identical circuit layout, including the X-shaped qubit capacitor and drive/gate lines and fabrication steps, ensuring a comparable electromagnetic environment. The zoom-in images of the Josephson junction areas, highlighted in blue and red, are shown in (b) and (c) for the gatemon and transmon, respectively. (b) The gatemon employs a superconductor–semiconductor–superconductor (S–Sm–S) hybrid Josephson junction based on InAs/Al nanowires. One segment of the Al shell is selectively etched to form the S–Sm–S weak link, as shown in the inset. (c) The transmon uses a conventional superconductor–insulator–superconductor (SIS) Josephson junction. Gate dielectric $\mathrm{HfO_x}$ (orange) is applied to both qubits to compare device performance under as similiar conditions as possible. (d) The primary loss mechanisms under investigation: the Purcell effect, spontaneous emission, internal loss, quasiparticle poisoning, and possible S–Sm–S-junction-specific loss, with corresponding relaxation rates labeled as $\Gamma_\mathrm{Pur}$, $\Gamma_\mathrm{spont}$, $\Gamma_\mathrm{int}$, $\Gamma_\mathrm{QPP}$, and $\Gamma_\mathrm{SSmS}$.
• Figure 2: Comparison of relaxation times between transmons and gatemons. (a) Energy relaxation measurement of a representative transmon. (b) Energy relaxation measurement of a representative gatemon at similar qubit frequencies to the fixed-frequency transmon in panel (a). Both qubits are located on the same chip (Chip 2). (c) Summary of $T_1$ times for all measured devices across four different chips. Chips 1--3 are fabricated using aluminum films, and Chip 4 uses a NbTiN film. Qubits on the same chip are indicated by the same marker shape, while different colors are used to distinguish individual qubits. The qubits are grouped into three categories: aluminum transmons, aluminum gatemons, and NbTiN gatemons, each represented by a distinct color palette. The red dashed line shows the extrapolated $T_1$ limit for a transmon with a constant quality factor $Q = 2\pi f T_1$, while the shaded region indicates the expected $T_1$ range for the best-performing gatemon extrapolated across frequencies.
• Figure 3: Gatemon relaxation time as a function of qubit frequency $f_q$. Dashed lines indicate the expected limits from Purcell decay, spontaneous emission through the gate line, and internal loss. The solid line shows the combined theoretical limit. The pronounced dip near $6.43GHz$ corresponds to the readout resonator frequency. The reduction in $T_{1}$ around $4.5GHz$ is attributed to a spurious two-level system (TLS), and is not a generic feature of our devices.
• Figure 4: Detailed gatemon qubit design. (a) Representative optical image of a gatemon qubit from this work. The gate line is placed $235µm$ away from the qubit capacitor (blue). Zoom in of the dashed box region is shown in (b). This segment of the gate line is designed to be $200nm$ wide. The ground plane is brought along with the gate line, the ground shielding, to shield the qubit from this line. (c) Circuit diagram of the qubit. The single gate line is in close proximity to the junction for effectively tuning the Josephson energy ($Z$ control), and serve as a drive line ($XY$ control) via optimized coupling capacitance to the qubit (see text for details).
• Figure 5: Qubit relaxation times $T_1$ as a function of temperature.$T_1$ measurements for a gatemon (blue) and a transmon (red) from Chip 2 at different temperatures. The gatemon is measured at two different qubit frequencies, $3.70GHz$ and $4.04GHz$. At base temperature ($30mK$), the transmon exhibits a relaxation time of approximately $25µs$, while the gatemon shows $T_1\approx4.5µs$ and $T_1\approx2.7µs$ for the high- and low-frequency configurations, respectively. The dashed lines are fits using a quasiparticle poisoning model, $T_1(T) = \bigl[\Gamma_0 + (\sqrt{8\Delta h f_{\mathrm{q}}}/h)\sqrt{2\pi k_{\mathrm{B}}T/\Delta}\, e^{-\Delta/(k_{\mathrm{B}}T)}\bigr]^{-1}$, where $\Gamma_0$ is the temperature-independent decay rate, $k_\mathrm{B}$ is the Boltzmann constant, and $\Delta$ is the superconducting gap.