Logo
ScienceStack
Table of Contents
Fetching ...
Sign In

Adaptive High-Speed Radar Signal Processing Architecture for 3D Localization of Multiple Targets on System on Chip

Aakanksha Tewari, Jai Mangal, Sumit J Darak, Shobha Sundar Ram, Arnav Shukla

Abstract

Integrated Sensing and Communication (ISAC) is a key enabler of high speed, ultra low latency vehicular communication in 6G. ISAC leverages radar signal processing (RSP) to localize multiple unknown targets amid static clutter by jointly estimating range, azimuth, and Doppler velocity (3D), thereby enabling highly directional beamforming toward intended mobile users. However, the speed and accuracy of RSP significantly impact communication throughput. This work proposes a novel 3D reconfigurable RSP accelerator, implemented on a Zynq Multi processor System on Chip (MPSoC) using a hardware software codesign approach and fixed point optimization. We propose two RSP frameworks: (1) high accuracy and high complexity, and (2) low complexity and low accuracy, along with their respective architectures. Then, we develop an adaptive architecture that dynamically switches between these two frameworks based on the signal to clutter plus noise ratio. This adaptive reconfiguration achieves up to 5.6 times faster RSP compared to state of the art designs. At the system level, the proposed RSP based ISAC delivers a 24% improvement in communication throughput without increasing hardware complexity.

Adaptive High-Speed Radar Signal Processing Architecture for 3D Localization of Multiple Targets on System on Chip

Abstract

Integrated Sensing and Communication (ISAC) is a key enabler of high speed, ultra low latency vehicular communication in 6G. ISAC leverages radar signal processing (RSP) to localize multiple unknown targets amid static clutter by jointly estimating range, azimuth, and Doppler velocity (3D), thereby enabling highly directional beamforming toward intended mobile users. However, the speed and accuracy of RSP significantly impact communication throughput. This work proposes a novel 3D reconfigurable RSP accelerator, implemented on a Zynq Multi processor System on Chip (MPSoC) using a hardware software codesign approach and fixed point optimization. We propose two RSP frameworks: (1) high accuracy and high complexity, and (2) low complexity and low accuracy, along with their respective architectures. Then, we develop an adaptive architecture that dynamically switches between these two frameworks based on the signal to clutter plus noise ratio. This adaptive reconfiguration achieves up to 5.6 times faster RSP compared to state of the art designs. At the system level, the proposed RSP based ISAC delivers a 24% improvement in communication throughput without increasing hardware complexity.

Paper Structure

This paper contains 37 sections, 13 equations, 24 figures, 11 tables.

Table of Contents

  1. Introduction
  2. RSP System Model and Algorithm
  3. MJARP vs JARP
  4. JARP
  5. Modified Joint Azimuth-Range Processing (MJARP)
  6. Sequential Azimuth-Range Processing (SARP)
  7. Computational Complexity Comparison
  8. Doppler Velocity Estimation
  9. Mapping of Algorithms to Architecture
  10. Range-Azimuth Localization on first packet with SARP
  11. Time Domain Matched Filtering
  12. Frequency Domain Matched Filtering
  13. Range-Azimuth Localization on first packet with MJARP
  14. Extension to Multiple Targets (SARP/MJARP)
  15. Multi-Packet Range-Azimuth Localization (SARP/MJARP)
  16. ...and 22 more sections

Figures (24)

  • Figure 1: DBF and MF for RA localization of $n^{th}$ target with (a) MJARP for first $(m=0)$ packet, (b) SARP for first $(m=0)$ packet, (c) MJARP and SARP for next $(M-1)$ packets
  • Figure 2: Reconfigurable RSP on Zynq MPSoC via HSCD.
  • Figure 3: Hardware architecture for SARP DBF.
  • Figure 4: Hardware architecture for SARP (a)TD-MF, (b)FD-MF.
  • Figure 5: Hardware architecture for MJARP MF and DBF.
  • ...and 19 more figures