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AXON: An Automated Netlist Optimization Framework for High-Speed Adders

Tiantian Yang, Xuanle Ren, Qingdian Wan, Qi Meng

Abstract

Adders are fundamental building blocks in modern digital systems, and their performance, power, and area (PPA) directly impact system efficiency. Contemporary adders typically use parallel-prefix architectures with established PPA trade-offs, but these often fail to deliver globally optimal PPA for specific design goals. Prior work lacks netlist-/cell-level awareness, and general synthesis heuristics are not adder-specific, resulting in suboptimal PPA. To address this, we propose AXON, an automated netlist optimization framework for adders. It performs design space exploration from architectural to netlist level, integrating prefix topology search with standard-cell-aware mapping via a hierarchical approach to quickly converge to near-optimal PPA solutions. We also introduce a hybrid ultra-high-speed adder combining parallel-prefix and Ling architectures to shorten the critical path. Experiments on TSMC 28nm library show AXON improves delay, area-delay product, and energy-delay product by up to 10.3%, 12.6%, and 32.1% respectively, compared to commercial synthesis tools.

AXON: An Automated Netlist Optimization Framework for High-Speed Adders

Abstract

Adders are fundamental building blocks in modern digital systems, and their performance, power, and area (PPA) directly impact system efficiency. Contemporary adders typically use parallel-prefix architectures with established PPA trade-offs, but these often fail to deliver globally optimal PPA for specific design goals. Prior work lacks netlist-/cell-level awareness, and general synthesis heuristics are not adder-specific, resulting in suboptimal PPA. To address this, we propose AXON, an automated netlist optimization framework for adders. It performs design space exploration from architectural to netlist level, integrating prefix topology search with standard-cell-aware mapping via a hierarchical approach to quickly converge to near-optimal PPA solutions. We also introduce a hybrid ultra-high-speed adder combining parallel-prefix and Ling architectures to shorten the critical path. Experiments on TSMC 28nm library show AXON improves delay, area-delay product, and energy-delay product by up to 10.3%, 12.6%, and 32.1% respectively, compared to commercial synthesis tools.

Paper Structure

This paper contains 14 sections, 15 equations, 8 figures, 1 table, 1 algorithm.

Table of Contents

  1. Introduction
  2. Parallel Prefix Adders and Existing Optimization Techniques
  3. Parallel Prefix Adders
  4. Existing PPA Design and Optimization Techniques
  5. Methodology
  6. AXON Overview
  7. Hybrid Parallel-Prefix–Ling Adder Architecture
  8. Insertion of Propagate Gates and Inverters
  9. Design Space Exploration
  10. Evaluation
  11. Evaluation of Hybrid Parallel-Prefix and Ling Architecture
  12. Design Space Exploration Results
  13. Fine-Grained Evaluation Results
  14. Conclusion

Figures (8)

  • Figure 1: (a)–(c) Prefix topologies of representative adders. (d) Comparison of different adders (adapted from Weste2004).
  • Figure 2: AXON Overview.
  • Figure 3: Conversion between standard prefix nodes and Ling nodes.
  • Figure 4: Different inverter insertion strategies. Solid nodes represent positive polarity, while hollow nodes represent negative polarity. If nodes of the same polarity are connected, it means an inverter needs to be inserted on that edge. This figure shows reducing the number of inverters may increase the critical path.
  • Figure 5: Traversal method for inverter insertion: nodes requiring inversion (marked by stars) are grouped into independent clusters, and inverter positions are traversed within each cluster.
  • ...and 3 more figures