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First Demonstration of 28 nm Fabricated FeFET-Based Nonvolatile 6T SRAM

Albi Mema, Simon Thomann, Narendra Singh Dhakad, Hussam Amrouch

Abstract

With the staggering increase of edge compute applications like Internet-of-Things (IoT) and artificial intelligence (AI), the demand for fast, energy-efficient on-chip memory is growing. While the fast and mature static random-access memory (SRAM) technology is the standard choice, its volatility requires a constant supply voltage to operate and store data. Especially in edge AI and IoT devices that often idle, the leakage power consumes a significant portion of the constrained power budget. For this, emerging non-volatile memory (NVM) technologies such as Resistive RAM and ferroelectric FET (FeFET) offer zero-standby power consumption but suffer from integration and performance tradeoffs. To harness the benefits of the different technologies, hybrid architectures have been proposed, combining SRAM with NVM devices. This work proposes a hybrid non-volatile SRAM (nvSRAM) architecture based on recently demonstrated PMOS FeFETs (p-FeFETs). By replacing the two PMOS pull-up transistors with p-FeFETs, we achieve non-volatility without additional transistors. The design supports seamless power-down and restore operation, thus eliminating standby leakage. SPICE simulations in a commercial 28 nm technology show read latency comparable to conventional SRAM, and on-silicon measurements show robust restore behavior. With this, we are the first to demonstrate a fabricated 6T nvSRAM cell design. The resulting cell achieves an area footprint of 99 $μm^2$. The read path remains identical to baseline SRAM, enabling high-speed operation while being non-volatile, making it ideal for IoT and edge systems.

First Demonstration of 28 nm Fabricated FeFET-Based Nonvolatile 6T SRAM

Abstract

With the staggering increase of edge compute applications like Internet-of-Things (IoT) and artificial intelligence (AI), the demand for fast, energy-efficient on-chip memory is growing. While the fast and mature static random-access memory (SRAM) technology is the standard choice, its volatility requires a constant supply voltage to operate and store data. Especially in edge AI and IoT devices that often idle, the leakage power consumes a significant portion of the constrained power budget. For this, emerging non-volatile memory (NVM) technologies such as Resistive RAM and ferroelectric FET (FeFET) offer zero-standby power consumption but suffer from integration and performance tradeoffs. To harness the benefits of the different technologies, hybrid architectures have been proposed, combining SRAM with NVM devices. This work proposes a hybrid non-volatile SRAM (nvSRAM) architecture based on recently demonstrated PMOS FeFETs (p-FeFETs). By replacing the two PMOS pull-up transistors with p-FeFETs, we achieve non-volatility without additional transistors. The design supports seamless power-down and restore operation, thus eliminating standby leakage. SPICE simulations in a commercial 28 nm technology show read latency comparable to conventional SRAM, and on-silicon measurements show robust restore behavior. With this, we are the first to demonstrate a fabricated 6T nvSRAM cell design. The resulting cell achieves an area footprint of 99 . The read path remains identical to baseline SRAM, enabling high-speed operation while being non-volatile, making it ideal for IoT and edge systems.

Paper Structure

This paper contains 7 sections, 3 figures, 2 tables.

Table of Contents

  1. Introduction
  2. Background
  3. Baseline 6T SRAM
  4. State-of-the-art nvSRAM Design
  5. FeFET as an Emerging Non-Volatile Memory
  6. Design of Our Proposed nvSRAM Cell
  7. Write Operation

Figures (3)

  • Figure 1: Circuit diagram of (a) our proposed 6T , (b) baseline 6T , (c) 8T UCB, and (d) 10T 8T2F. Here, the transistors highlighted in orange are .
  • Figure 2: (a) Conventional high positive gate voltage write. The high potential difference from the gate to the grounded source and drain polarizes the ferroelectric layer to HVT. (b) Conventional high negative gate voltage write. This voltage polarizes the ferroelectric to LVT. (c) Source-drain write is employed by the proposed design. This scheme omits the need for negative voltages. (d) Gate-drain write employed by the proposed design. The polarization mainly occurs on the gate-to-drain side of the transistor. On average, the ferroelectric layer polarizes to HVT.
  • Figure 3: Comparison of $I_{\text{D}}\xspace\text{-}V_{\text{G}}\xspace$ characteristics between the conventional gate programming scheme and drain programming scheme. The mw measures the difference between the LVT and HVT states.