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IBEX: Internal Bandwidth-Efficient Compression Architecture for Scalable CXL Memory Expansion

Younghoon Ko, Hyemin Park, Hyuk-Jae Lee, Hyokeun Lee

Abstract

As the memory channel count is confined by physical dimensions, memory expanders appear to be a promising approach to extending memory capacity and channels by augmenting the existing I/O interface (e.g., PCIe) with memory-semantic protocols like CXL. Unfortunately, the physical constraints of a computing system restrict scalable capacity expansion with memory expanders. In this work, we propose a block-level compression scheme for modern memory expanders, IBEX, to achieve larger effective memory capacity. Given the performance overhead associated with block-level compression algorithms (e.g., LZ77), IBEX employs a promotion-based approach: only cold data is compressed, whereas hot data remains uncompressed. Our key innovation is internal bandwidth-efficient block management that precisely identifies cold pages with minimal metadata access overhead. Still, the promotion-based approach poses several performance-related challenges at the design level. Therefore, we also propose a shadowed promotion scheme that temporarily postpones the deallocation of promoted data, thereby mitigating the performance penalty incurred by demotion (i.e., recompression). Furthermore, we optimize our compression scheme by compacting metadata and co-locating multiple target blocks for efficient bandwidth utilization. Consequently, IBEX achieves an average of 1.28x-1.40x speedups compared to the state-of-the-art promotion-based block-level approaches. We open-source IBEX at https://github.com/relacslab/ibex-ics26.

IBEX: Internal Bandwidth-Efficient Compression Architecture for Scalable CXL Memory Expansion

Abstract

As the memory channel count is confined by physical dimensions, memory expanders appear to be a promising approach to extending memory capacity and channels by augmenting the existing I/O interface (e.g., PCIe) with memory-semantic protocols like CXL. Unfortunately, the physical constraints of a computing system restrict scalable capacity expansion with memory expanders. In this work, we propose a block-level compression scheme for modern memory expanders, IBEX, to achieve larger effective memory capacity. Given the performance overhead associated with block-level compression algorithms (e.g., LZ77), IBEX employs a promotion-based approach: only cold data is compressed, whereas hot data remains uncompressed. Our key innovation is internal bandwidth-efficient block management that precisely identifies cold pages with minimal metadata access overhead. Still, the promotion-based approach poses several performance-related challenges at the design level. Therefore, we also propose a shadowed promotion scheme that temporarily postpones the deallocation of promoted data, thereby mitigating the performance penalty incurred by demotion (i.e., recompression). Furthermore, we optimize our compression scheme by compacting metadata and co-locating multiple target blocks for efficient bandwidth utilization. Consequently, IBEX achieves an average of 1.28x-1.40x speedups compared to the state-of-the-art promotion-based block-level approaches. We open-source IBEX at https://github.com/relacslab/ibex-ics26.

Paper Structure

This paper contains 26 sections, 17 figures, 2 tables.

Table of Contents

  1. Introduction
  2. Background
  3. CXL and Memory Expander
  4. Data Compression Algorithms
  5. Design Considerations of Data Compression in a Memory Subsystem
  6. Motivation
  7. Physical Constraints of CXL Memory
  8. Challenges of Block-Level Compression
  9. Architecture
  10. Adapting Promotion-based Block-Level Compression to CXL Memory
  11. Memory Management
  12. Translation Metadata
  13. Limitations of Prior Promotion-based Block-Level Compression
  14. Our Goals
  15. Design of IBEX
  16. ...and 11 more sections

Figures (17)

  • Figure 1: Normalized performance of compressed CXL memory using dual-channel relative to ideal bandwidth case.
  • Figure 2: Normalized performance of compressed CXL memory with naive SRAM relative to uncompressed CXL memory.
  • Figure 3: The high-level procedures of promotion-based compression when accessing a compressed page.
  • Figure 4: Naive metadata entry format.
  • Figure 5: IBEX handling reference bit update (red) and demotion candidate selection (blue).
  • ...and 12 more figures