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Per-Bank Memory Bandwidth Regulation for Predictable and Performant Real-Time System

Connor Rudy Sullivan, Amin Mamandipoor, Cole Ridge Strickler, Heechul Yun

Abstract

Modern multicore system-on-chips (SoCs) share off-chip DRAM across cores, where bank-level interference can significantly degrade performance and threaten real-time guarantees. While prior work has focused on per-core bandwidth regulation, these approaches treat main memory as a monolithic resource and overlook DRAM's inherent bank-level parallelism. We show that DRAM interference is fundamentally a bank-level phenomenon. We characterize the guaranteed bandwidth of modern DRAM, demonstrate that it remains effectively constant across generations, and show how this limitation can be exploited by single-bank attacks. These results highlight the need for bank-aware memory management for predictable and efficient real-time systems. We design and implement a novel per-bank memory bandwidth regulator in an open-source RISC-V SoC and evaluate it using FireSim with both synthetic and real-world workloads. Our evaluation demonstrates that per-bank regulation effectively mitigates adversarial bank contention and achieves a 5.74x average throughput improvement for best-effort workloads over traditional bank-oblivious approaches while providing the same-level of performance isolation guarantees for real-time workloads.

Per-Bank Memory Bandwidth Regulation for Predictable and Performant Real-Time System

Abstract

Modern multicore system-on-chips (SoCs) share off-chip DRAM across cores, where bank-level interference can significantly degrade performance and threaten real-time guarantees. While prior work has focused on per-core bandwidth regulation, these approaches treat main memory as a monolithic resource and overlook DRAM's inherent bank-level parallelism. We show that DRAM interference is fundamentally a bank-level phenomenon. We characterize the guaranteed bandwidth of modern DRAM, demonstrate that it remains effectively constant across generations, and show how this limitation can be exploited by single-bank attacks. These results highlight the need for bank-aware memory management for predictable and efficient real-time systems. We design and implement a novel per-bank memory bandwidth regulator in an open-source RISC-V SoC and evaluate it using FireSim with both synthetic and real-world workloads. Our evaluation demonstrates that per-bank regulation effectively mitigates adversarial bank contention and achieves a 5.74x average throughput improvement for best-effort workloads over traditional bank-oblivious approaches while providing the same-level of performance isolation guarantees for real-time workloads.

Paper Structure

This paper contains 31 sections, 3 equations, 8 figures, 6 tables, 1 algorithm.

Table of Contents

  1. Introduction
  2. Background
  3. DRAM Structure
  4. Memory Bandwidth Regulation
  5. Guaranteed Memory Bandwidth
  6. Measuring Guaranteed Memory Bandwidth
  7. Reverse Engineering of DRAM Bank Map Functions
  8. Hardware Platforms and Found DRAM Bank Maps
  9. Bank-Aware Parallel Linked-List (PLL) Benchmark
  10. Evaluation Results
  11. Single-Bank Memory Performance Attack
  12. Methodology
  13. Effects on Synthetic Victim
  14. Effects on Real-world Applications
  15. Per-Bank DRAM Bandwidth Regulation
  16. ...and 16 more sections

Figures (8)

  • Figure 1: Measured bandwidth (logarithmic scale) of PLL benchmarks as a function of MLP
  • Figure 2: Victim (Bandwidth) slowdown and attacker bandwidth consumption of all-bank (AB) and single-bank (SB) attacks.
  • Figure 3: Victim (X-axis) slowdown caused by all-bank (AB) vs. single-bank (SB) attacks.
  • Figure 4: Rocket SoC with our DRAM bandwidth regulator
  • Figure 5: Effects of all-bank (AB) and single-bank (SB) DRAM bank attacks against the synthetic victim on FireSim.
  • ...and 3 more figures