FireBridge: Cycle-Accurate Hardware + Firmware Co-Verification for Modern Accelerators

Abstract

Hardware-firmware integration is becoming a productivity bottleneck due to the increasing complexity of accelerators, characterized by intricate memory hierarchies and firmware-intensive execution. While numerous verification techniques focus on early-stage, approximate modeling of such systems to speed up initial development, developers still rely heavily on FPGA emulation to integrate firmware with RTL/HLS hardware, resulting in significant delays in debug iterations and time-to-market. We present a fast, cycle-accurate co-verification framework that bridges production firmware and RTL/gate-level hardware. FIREBRIDGE enables firmware debugging, profiling, and verification in seconds using standard simulators such as VCS, Vivado Xsim, or Xcelium, by compiling the firmware for x86 and bridging it with simulated subsystems via randomized memory bridges. Our approach provides off-chip data movement profiling, memory congestion emulation, and register-level protocol testing, which are critical for modern accelerator verification. We demonstrate a speedup of up to 50x in debug iteration over the conventional FPGA-based flow for system integration between RTL/HLS and production firmware on various types of accelerators, such as systolic arrays and CGRAs, while ensuring functional equivalence. FIREBRIDGE accelerates system integration by supporting robust co-verification of hardware and firmware, and promotes a structured, parallel development workflow tailored for teams building heterogeneous computing platforms.

Figures (9)

• Figure 1: (a): Conventional HW/FW integration and debugging flow results in lengthy development cycles. (b):FireBridge allows the user to compile the firmware natively for x86 and link to the RTL or Netlist to perform behavioral or gate-level simulation through open-source and commercial tools. (c): Our approach wraps host-side firmware in DPI-C interfaces to enable integration with our generalized memory bridges, which interface with transactional SystemVerilog testbenches via an optional memory congestion emulator.
• Figure 2: Comparing conventional development of accelerator-based embedded systems and development with FireBridge. Prior work focuses on early modeling of accelerators. (A)FireBridge significantly shortens time spent on firmware development and integration testing with hardware on FPGA by allowing teams to directly test the final firmware in both cycle-accurate RTL/HLS verification. (B) It also enables testing the final firmware in gate-level simulation. (C) Our profiling features also allow measuring and debugging data movement issues against those expected from early modeling.
• Figure 3: Execution flow of hardware & firmware bridged via FireBridge during verification. Control flow begins in a standard SystemVerilog testbench where all initial blocks start together and execute in parallel. FireBridge is initialized as one of them. The primary initial block starts the firmware.Reading/writing hardware registers is done through the provided functions. DDR can be accessed through regular C pointers. Hardware subsystems, such as accelerators, access the memory maintained in the C domain through provided generic bridges.
• Figure 4: The representative accelerator-based system used to compare the time & resources required for traditional vs proposed hardware-firmware integration flows. A 2D systolic array of 8-bit multipliers and 32-bit accumulators is integrated with four AXI4 DMAs.
• Figure 5: Comparing the runtime of FPGA implementation flow using Vivado, vs simulation flow with FireBridge, as a proxy for the time user spends on an iteration of debugging hardware-firmware integration. A representative SoC (Fig. \ref{['fig:systolic']}, Section \ref{['subsec:systolic']}) with a systolic array of varying numbers of processing elements is taken through both flows to demonstrate the scalability of FireBridge with increasing design complexity. 2500 PEs is the largest design that fits in the FPGA.