Characterization of Off-wafer Pulse Communication in BrainScaleS Neuromorphic System

Abstract

Neuromorphic VLSI systems take inspiration from biology to enable efficient emulation of large-scale spiking neural networks and to explore new computational paradigms. To establish large neuromorphic systems, a sophisticated routing infrastructure is needed to communicate spikes between chips and to/from the host computer. For the BrainScaleS wafer-scale neuromorphic system considered in this work, especially the stimulation with input spikes and the recording of spikes is demanding, requiring high bandwidth and temporal resolution due to the accelerated emulation of neural dynamics 10.000 faster than biological real time. Here, we present a systematic characterization of the BrainScaleS off-wafer communication infrastructure implemented around Kintex7 FPGAs. The communication flow is characterized in terms of throughput, transmission delay, jitter and pulse loss. Further, we analyze the effect of the communication distortions (like pulse loss and jitter) on a neural benchmark model with highly varying spike activity. The presented methods and techniques for communication evaluation are general applicable and provide useful insights for the mapping of network models to the hardware such as the distribution of input spikes across communication channels.

Figures (16)

• Figure 1: BrainScaleS system: (a) 3D-schematic of a BrainScaleS wafer module (dimensions: 50 cm × 50 cm × 15 cm) hosting the wafer (A) and 48 FPGAs (B). The positioning mask (C) is used to align elastomeric connectors that link the wafer to the large main PCB (D). Support PCBs provide power supply (E & F) for the on-wafer circuits as well as access (G) to analog dynamic variables such as neuron membrane voltages. The connectors for inter-wafer (USB slots) and off-wafer/host connectivity (Gigabit-Ethernet slots) are distributed over all four edges (H) of the main PCB. Mechanical stability is provided by an aluminum frame (I). © [2017] IEEE. Reprinted with permission from schmitt2017neuromorphic. (b) Photograph of fully assembled wafer module with wafer-IO-board and Kintex-7 FPGA board.
• Figure 2: The schematic of the Layer-2 network with an FPGA Kintex-7 is interfaced with eight HICANNs on the wafer and seven surrounding FPGA nodes.
• Figure 3: The used frame format of the application layer (AL) for the playback memory. In this example the payload is one pulse group with a shared FPGA release time and N pulse with a 14-bit label and 15-bit timestamp considered in the HICANN.
• Figure 4: The verification scheme for the evaluation of the BrainScaleS off-wafer routing. Characterization of the upstream: The HICANNs generate either regular or pseudo-random spike trains which are transmitted to the FPGA and recorded to the Trace memory. Characterization of the downstream: Pre-generated input pulses with release timestamps are first stored in the Playback memory from where they are transmitted to the wafer. In the HICANNs they are looped back with a new timestamp to be recorded by the Trace module. Afterwards, the received and applied spike trains are analyzed on the host to assess the effects of the off-wafer communication.
• Figure 5: Pulse throughput (a) and pulse loss (b) with regular and pseudo-random spike trains generated by background generators on the HICANN chip. The measurement concerns one link for the upstream flow. The calculation of the throughput assumes 24 bits per pulse.