Understanding Bugs in Quantum Simulators: An Empirical Study

Abstract

Quantum simulators are a foundational component of the quantum software ecosystem. They are widely used to develop and debug quantum programs, validate compiler transformations, and support empirical claims about correctness and performance. In the absence of large-scale quantum hardware, simulator outputs are often treated as ground truth for algorithm development and system evaluation. However, quantum simulators also introduce unique implementation challenges. They must faithfully emulate quantum behavior while executing on classical hardware, requiring complex representations of quantum state evolution, operator composition, and noise modeling. Yet, we still lack a large-scale and in-depth study of failures in quantum simulators. To bridge this gap, this work presents a comprehensive empirical study of bugs in widely used open-source quantum simulators. We analyze 394 confirmed bugs from 12 simulators and manually categorize them based on root causes, failure manifestations, affected components, and discovery mechanisms. Our study reveals several key findings. First, bug discovery is largely user-driven, with most crashes, exceptions, and resource-related failures not detected by automated testing and identified after deployment. Second, logical correctness failures are widespread and often silent, producing plausible but incorrect outputs without triggering crashes or explicit error signals. Third, many critical failures originate in classical simulator infrastructure, such as memory management, indexing, configuration, and dependency compatibility, rather than in core quantum execution logic. These findings provide new insights into the reliability challenges of quantum simulators and highlight opportunities to improve testing and validation practices in the quantum software ecosystem.

Figures (20)

• Figure 1: Typical architecture of quantum simulators, showing user-facing interfaces, circuit preparation, simulation backend, and supporting classical layers for acceleration and infrastructure.
• Figure 2: Overview of the data collection and analysis methodology, illustrating the multi-stage pipeline from initial project selection to the final taxonomic analysis of issues.
• Figure 3: An example feature request, which requests support for a multi-controlled SWAP gate.
• Figure 4: Qiskit Aer issue #416 shows error where incorrect loop bounds led to array boundary violations.
• Figure 5: Qulacs issue #632 demonstrates a core algorithmic flaw where the optimizer incorrectly merged parametric gates.