Benchmarking Dual-Polarization Silicon Nitride Photonic Integrated Circuits for Trapped-Ion Quantum Technologies

Abstract

Trapped ions are one of the most advanced platforms for quantum technologies, with applications ranging from quantum computing to precision timekeeping. A crucial step towards more compact and scalable systems involves integrating photonic integrated circuits (PICs) into surface ion traps to enable on-chip light delivery and optical addressing of individual ions. Currently, most implementations rely solely on transverse-electric (TE) mode grating couplers, where the emitted light is polarized in the plane of the chip. In this work, we design, fabricate and characterize silicon nitride (Si\(_3\)N\(_4\)) PIC components, including incoupling structures, splitters, and grating couplers that support both TE and transverse-magnetic (TM) modes with comparable optical losses. We benchmark the PIC at 760\,nm, which is a typical wavelength for Yb$^{+}$-applications. The fabricated grating couplers enable the outcoupling of collimated free-space beams for both polarizations, exhibiting distinct emission angles. This dual-polarization capability gives more flexibility in polarization control and expands the accessible optical design space for trapped-ion quantum technologies.

Figures (6)

• Figure 1: a) Optical micrograph of the fabricated Si$_3$N$_4$ PIC, showing different functional regions: WG cutback structures (purple), bend and bend-shift loss structures (cyan), EBL–OL taper structures (yellow), grating coupler (green) and splitter test structures (orange)). b) Targeted multilayer stack. From bottom to top: Si substrate, SiO$_2$ BOX (L-1), Si$_3$N$_4$ WG-GC (L-2) and WG for light incoupling layers (L-4) separated by a 1.25 $\upmu$m thick SiO$_2$ buffer layer (L-3). Above these, an additional SiO$_2$ buffer layer is followed by a gold ground plane, 3 $\upmu$m thick SiO$_2$ spacer, and a top gold layer used as the electrodes. Holes in the electrodes are covered with an ITO layer. The red cone illustrates the beam emitted by the GC.
• Figure 2: Schematics of vertical fiber-to-chip coupling scheme. (a) Illustration of the fiber-to-chip edge coupling into the PIC. (b) Geometry of the two-layer adiabatic taper for efficient mode conversion between L-4 and L-2 waveguides. (c) Schematic of the EBL-to-OL coupling stage. The red arrows depict the light propagation through the structures.
• Figure 3: a) Schematic illustration of the optical characterization setup. The red cone illustrates the beam emitted from the PIC. b) Cutback measurement to deduce the coupling and propagation losses for the TE and TM modes at a wavelength of 760 nm. Data points shown with reduced opacity were excluded from the fit. c) Characterization of the EBL–OL transition taper, showing the extracted taper loss. The inset displays the cascaded taper section.
• Figure 4: Per-bend loss for the TE a) and TM b) polarization, comparing standard bends to laterally shifted bend geometries across different bend radii. In the shifted designs, $\Lambda$ denotes the lateral offset, as illustrated in the inset of a). c) Measured attenuation of cascaded MMI splitters for the TE and TM modes. The linear fits provide the attenuation per MMI device and include additional contributions from bend and propagation losses.
• Figure 5: a) Schematic illustration of the two beams emitted from the GC, corresponding to orthogonal TE and TM polarizations. b) Top-view optical microscope image of the fabricated Si$_3$N$_4$/SiO$_2$ GC. (c,e) Simulated far-field intensity distributions as a function of emission angle, evaluated in a plane 100 $\upmu$m above the chip surface, for TE and TM polarizations, respectively. (d,f) Experimental intensity maps acquired from 25 $\upmu$m to 150 $\upmu$m above the chip surface were fitted to reconstruct the emission profiles of the GC for TE and TM polarizations, respectively.