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Self-Heating and Parasitic Effects in Multi-Tier CFET Design

Sufia Shahin, Mahdi Benkhelifa, Yogesh Singh Chauhan, Hussam Amrouch

Abstract

In this article, we study the impact of self-heating effects (SHEs) and middle of line (MOL) and back-end of line (BEOL) induced parasitics on multi-tier CFET design, where multiple nanosheet devices are vertically stacked. We analyze and compare the 4-tier CFET design with the conventional 2-tier CFET, using TCAD models calibrated to experimental measurements. Additionally, TCAD simulations are used to model and analyze SHE-induced heat distribution and temperature profiles and to extract the detailed parasitic RC network from 3D models of CMOS inverters designed with full MOL and BEOL interconnects. At the device level, the maximum temperature rise (TMAX) caused by SHE in nFET and pFET devices of the 2-tier CFET architecture is 62 K and 74 K, respectively. Due to the increased distance from the substrate heat sink, the upper-tier nFET and pFET devices in the 4-tier design show higher TMAX of 83.5 K and 98.5 K and more heat trapping in the stacked layers. Furthermore, in the 4-tier CFET-based CMOS inverters, the BEOL-induced parasitic RCs are, respectively, 10 and 6.5 times higher in the top-tier than in the 2-tier CFET-based inverters. In the bottom tier, the corresponding parasitic RC elements are 6.26 and 2 times higher, respectively, than in the 2-tier inverters. Finally, compared to the 4-tier design without parasitics, the propagation delay of the top and bottom tier inverters increases by 10% and 8.2%, respectively, due to the interconnect parasitic RCs. For the conventional 2-tier inverter, the corresponding degradation of delay with parasitic RCs is 37.25%.

Self-Heating and Parasitic Effects in Multi-Tier CFET Design

Abstract

In this article, we study the impact of self-heating effects (SHEs) and middle of line (MOL) and back-end of line (BEOL) induced parasitics on multi-tier CFET design, where multiple nanosheet devices are vertically stacked. We analyze and compare the 4-tier CFET design with the conventional 2-tier CFET, using TCAD models calibrated to experimental measurements. Additionally, TCAD simulations are used to model and analyze SHE-induced heat distribution and temperature profiles and to extract the detailed parasitic RC network from 3D models of CMOS inverters designed with full MOL and BEOL interconnects. At the device level, the maximum temperature rise (TMAX) caused by SHE in nFET and pFET devices of the 2-tier CFET architecture is 62 K and 74 K, respectively. Due to the increased distance from the substrate heat sink, the upper-tier nFET and pFET devices in the 4-tier design show higher TMAX of 83.5 K and 98.5 K and more heat trapping in the stacked layers. Furthermore, in the 4-tier CFET-based CMOS inverters, the BEOL-induced parasitic RCs are, respectively, 10 and 6.5 times higher in the top-tier than in the 2-tier CFET-based inverters. In the bottom tier, the corresponding parasitic RC elements are 6.26 and 2 times higher, respectively, than in the 2-tier inverters. Finally, compared to the 4-tier design without parasitics, the propagation delay of the top and bottom tier inverters increases by 10% and 8.2%, respectively, due to the interconnect parasitic RCs. For the conventional 2-tier inverter, the corresponding degradation of delay with parasitic RCs is 37.25%.
Paper Structure (6 sections, 7 figures, 3 tables)

This paper contains 6 sections, 7 figures, 3 tables.

Table of Contents

  1. INTRODUCTION
  2. TCAD Device Modeling and Calibration
  3. Self-Heating Analysis in Multi-Tier CFET Design
  4. Impact of SHE at Device Level
  5. Self-Heating Analysis at Circuit Level
  6. Impact of Multi-Tier Design on BEOL Parasitics

Figures (7)

  • Figure 1: 3D TCAD models of the vertically stacked (a) conventional 2-tier CFET and (b) 4-tier CFET devices. Multi-tiering can improve density as an alternative to CPP scaling by means of vertical stacking. The physical dimensions of the TCAD models are listed in \ref{['table:parameters']}.
  • Figure 2: The transfer characteristics of our 2-tier CFET model are calibrated in linear (VDS=50 mV) and saturation (VDS=0.75 V) regimes of operation to the experimental measurements liao2023complementary.
  • Figure 3: Heatmaps generated for (a) nFET and (b) pFET devices, due to SHE, in the 2-tier CFET design extracted using TCAD simulations invoking the thermodynamic transport model and thermal conductivities sourced from heat1heat2. The devices are biased to turn on individually.
  • Figure 4: SHE induced heatmaps generated for the individually turned on nFET and pFET devices in (a), (b) bottom-tier and (c), (d) top-tier of the 4-tier CFET. Top-tier devices exhibit more heating and rise in temperature than the bottom-tier devices due to a larger distance from the substrate.
  • Figure 5: (a) Impact of SHE on 2-tier CFET IDS-VGS characteristics, with 14% ION degradation in nFET and 24% in pFET. Effect of SHE on the DC characteristics of (b) the bottom- and (c) top-tier devices, respectively. (d) Transfer characteristics compared for the bottom- and top-tier devices. Top-tier devices exhibit better drive strength than the bottom-tier devices.
  • ...and 2 more figures