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Gate-Drain Leakage Enhanced by Drain-Induced Dielectric Barrier Lowering in Gate-All-Around Field Effect Transistors

Juan P. Mendez, Coleman Cariker, Michael Titze, Alex A. Belianinov, Denis Mamaluy

Abstract

Gate-All-Around Field-Effect Transistors (GAAFETs), now entering high-volume production as successors to fin field-effect transistor technology, are enabling continued scaling and enhanced performance in advanced semiconductor nodes. However, the drain-current in GAAFETs strongly deviates from the thermionic dependence at negative gate voltages, exhibiting the existence of leakage that is additionally enhanced at high applied biases. Understanding the origin of this leakage is essential for determining the scaling limits of GAAFETs and for guiding device and material optimizations aimed at suppressing the off-state current. Additionally, recent experimental measurements have revealed the increased influence of radiation-induced defects in the negative gate voltage regime, with their impact remaining largely negligible for positive gate voltages. Through predictive first-principles simulations, we demonstrate that the observed leakage current at negative gate voltages originates from gate-to-drain tunneling, which is significantly enhanced by drain-induced dielectric barrier lowering between the gate and drain.

Gate-Drain Leakage Enhanced by Drain-Induced Dielectric Barrier Lowering in Gate-All-Around Field Effect Transistors

Abstract

Gate-All-Around Field-Effect Transistors (GAAFETs), now entering high-volume production as successors to fin field-effect transistor technology, are enabling continued scaling and enhanced performance in advanced semiconductor nodes. However, the drain-current in GAAFETs strongly deviates from the thermionic dependence at negative gate voltages, exhibiting the existence of leakage that is additionally enhanced at high applied biases. Understanding the origin of this leakage is essential for determining the scaling limits of GAAFETs and for guiding device and material optimizations aimed at suppressing the off-state current. Additionally, recent experimental measurements have revealed the increased influence of radiation-induced defects in the negative gate voltage regime, with their impact remaining largely negligible for positive gate voltages. Through predictive first-principles simulations, we demonstrate that the observed leakage current at negative gate voltages originates from gate-to-drain tunneling, which is significantly enhanced by drain-induced dielectric barrier lowering between the gate and drain.
Paper Structure (4 sections, 1 equation, 5 figures, 1 table)

This paper contains 4 sections, 1 equation, 5 figures, 1 table.

Table of Contents

  1. Introduction
  2. Results and discussion
  3. Conclusions
  4. Methodology

Figures (5)

  • Figure 1: Schematic representation of the technology transition from FinFET to next-generation GAAFET architecture.
  • Figure 2: (a) Measured drain-current/gate-voltage characteristics in Ref. Loubet:2017 for a 44 nm-CPP GAAFET at two drain biases of $V_d=0.05$ and $0.7$ V, corresponding to the linear and saturation region operations, respectively, together with the simulated characteristics for an ideal-operation GAAFET shown in (b). Measured current reprinted with permission from Ref. Loubet:2017. (b) Cross-section schematic of the simulated single-sheet GAAFET used for the ideal operation, in which gate leakage is negligible. $T_{Si}$ represents the thickness of the silicon channel.
  • Figure 3: (a) Effective potentials along the device channel for several gate voltages, illustrating how the channel effective-potential barrier change with the gate voltage. The applied drain bias is $V_d=0.7$ V. The inset illustrates the source-drain current spectrum $j_{SD}(E)$, indicating the corresponding thermionic and tunneling contributions. (b) Effective potentials along the channel for two distinct drain biases, $V_d=0.05$ and $0.7$ V, illustrating the DIBL (drain-induced barrier lowering) effect commonly observed in short-channel devices.
  • Figure 4: (a) Cross-section schematic of the single-sheet GAAFET device used in this work to investigate the gate leakage. $I-V_{g}$ characteristics and the corresponding gate leakage current contributions for $V_d=0.05$ V in (b) and $V_d=0.7$ V in (c). Measured current reprinted with permission from Ref. Loubet:2017
  • Figure 5: Contour-color maps of the effective potential for $V_d=0.05$ V in (a) and for $V_d=0.7$ V in (b). (c) Effective potential along the line drawn in (a,b) between gate and source for a $V_d$ of 0.05 and 0.7 V. (d) Effective potential along the line drawn in (a,b) between gate and drain for a $V_d$ of 0.05 and 0.7 V. The gate voltage for all cases (a-d) is $V_g=-0.3$ V.