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Adaptive Parallelism-Aware Qubit Routing for Ion Trap QCCD Architectures

Anabel Ovide, Andreu Angles-Castillo, Carmen G. Almudever

Abstract

Trapped-ion Quantum Charge-Coupled Device (QCCD) architectures promise scalability through interconnected trap zones and dynamic ion transport; however, this transport capability creates a complex compilation challenge: how to move qubits efficiently without degrading fidelity. We introduce a routing strategy that turns this challenge into an advantage by exploiting operational parallelism across traps while adapting to both algorithmic structure and device topology through a configurable multi-parameter scoring mechanism. Across a broad suite of benchmarks and QCCD layouts, the method consistently reduces ion-transport overhead and improves execution fidelity, outperforming state-of-the-art routing techniques. These results highlight that explicitly balancing movement overhead and execution parallelism under architectural constraints is key to unlocking the full potential of modular trapped-ion quantum processors.

Adaptive Parallelism-Aware Qubit Routing for Ion Trap QCCD Architectures

Abstract

Trapped-ion Quantum Charge-Coupled Device (QCCD) architectures promise scalability through interconnected trap zones and dynamic ion transport; however, this transport capability creates a complex compilation challenge: how to move qubits efficiently without degrading fidelity. We introduce a routing strategy that turns this challenge into an advantage by exploiting operational parallelism across traps while adapting to both algorithmic structure and device topology through a configurable multi-parameter scoring mechanism. Across a broad suite of benchmarks and QCCD layouts, the method consistently reduces ion-transport overhead and improves execution fidelity, outperforming state-of-the-art routing techniques. These results highlight that explicitly balancing movement overhead and execution parallelism under architectural constraints is key to unlocking the full potential of modular trapped-ion quantum processors.
Paper Structure (27 sections, 5 equations, 12 figures, 3 tables, 2 algorithms)

This paper contains 27 sections, 5 equations, 12 figures, 3 tables, 2 algorithms.

Figures (12)

  • Figure 1: Example of compiling a quantum circuit onto a 1D linear topology consisting of two 4-ion capacity traps. Left: original circuit. Center: compiled circuit with an added SWAP and Shuttle. Right: compiling process (from top to bottom), (i) initial allocation of three ions in each trap, enabling the first two CX gates (executed in parallel), (ii) SWAP to move qubit 2 to the trap edge, and (iii) Shuttle to the adjacent trap to perform the remaining CX gates.
  • Figure 2: Flow diagram illustrating the steps of the proposed routing algorithm.
  • Figure 3: Example of the trap selection process. (i) Shortest paths are computed (top left), (ii) trap scores are evaluated (top right), (iii) the highest-scoring trap is selected and ion movements applied (bottom left), (iv) and the resulting movements and positions are recorded (bottom right).
  • Figure 4: Example of congested-trap resolution (top to bottom). (i) The trap highlighted in green must free one slot ($EC=0$), but the adjacent trap along the relocation path is also full. The shortest path to the nearest trap with available capacity ($EC>0$) is identified. (ii) Ions in the adjacent trap are scored using the relocation metric, and the highest-scoring movable ion is selected. (iii) The selected ion is shuttled to the trap with free capacity, propagating space backward along the path. (iv) All ion movements and updated positions are recorded.
  • Figure 5: Topologies used in the analysis: linear array (top; L), ring structure (middle; R), and grid topology (bottom; H), each consisting of eight traps with a capacity of six ions.
  • ...and 7 more figures