Logo
ScienceStack
Table of Contents
Fetching ...
Sign In

A Sub-electron-noise Skipper-CCD Readout ASIC with Improved Channel-to-channel Isolation and an Integrated Cryogenic Voltage Reference

Fabricio Alcalde Bessia, Claudio Chavez, Troy England, Hongzhi Sun, Andrew Lathrop, Davide Braga, Miguel Sofo-Haro, Juan Estrada, Farah Fahim

Abstract

The MIDNA application specific integrated circuits (ASICs) are a series of skipper-CCD readout chips fabricated in a 65 nm low-power CMOS process that implement a correlated double sampling signal processing chain based on dual-slope integrators. They are capable of working from room to cryogenic temperatures, down to 84 K. The present iteration of the ASIC has been fabricated including several design updates and the addition of an on-chip voltage reference, resulting in improved performance. This work presents the main vulnerabilities solved, the changes carried out, and the resulting performance benefits. Measurements with a skipper-CCD and the ASIC at 140 K showed that the single-electron resolution can be reached by averaging the measured charge in the analog domain using the analog pile-up technique with a readout noise as low as 0.11 erms of equivalent charge for 1200 samples. The channel-to-channel crosstalk was also characterized showing values better than -62 dB.

A Sub-electron-noise Skipper-CCD Readout ASIC with Improved Channel-to-channel Isolation and an Integrated Cryogenic Voltage Reference

Abstract

The MIDNA application specific integrated circuits (ASICs) are a series of skipper-CCD readout chips fabricated in a 65 nm low-power CMOS process that implement a correlated double sampling signal processing chain based on dual-slope integrators. They are capable of working from room to cryogenic temperatures, down to 84 K. The present iteration of the ASIC has been fabricated including several design updates and the addition of an on-chip voltage reference, resulting in improved performance. This work presents the main vulnerabilities solved, the changes carried out, and the resulting performance benefits. Measurements with a skipper-CCD and the ASIC at 140 K showed that the single-electron resolution can be reached by averaging the measured charge in the analog domain using the analog pile-up technique with a readout noise as low as 0.11 erms of equivalent charge for 1200 samples. The channel-to-channel crosstalk was also characterized showing values better than -62 dB.
Paper Structure (9 sections, 2 equations, 10 figures)

This paper contains 9 sections, 2 equations, 10 figures.

Table of Contents

  1. Introduction
  2. ASIC Design and Improvements
  3. Reference Buffer Design
  4. Bandgap Reference Design
  5. Measurements
  6. Crosstalk measurements
  7. Integrator offset measurements
  8. Bandgap reference measurements
  9. Summary and conclusions

Figures (10)

  • Figure 1: Comparison between the signal paths in the previous iteration (top) and the current work (bottom). Each chip includes four channels.
  • Figure 2: Photo of the present ASIC. Its size is 2.5 by 1. The main blocks are: (1) Preamplifier, (2) reference-voltage buffer, (3) DC restorer, (4) signal buffer, (5) integrator, (6) bias generators, and (7) bandgap reference.
  • Figure 3: Timing diagram showing the control signals along with the CCD output and intermediate signals of the channel. Adapted from alcalde2023noise.
  • Figure 4: Simulated crosstalk between two channels of the previous chip due to shared resistance to the reference voltage.
  • Figure 5: Schematic of the reference buffer implemented for each channel.
  • ...and 5 more figures