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A Minimal-Component 100 MHz Full-Duplex Digital Link Over a Single Coaxial Cable for Laboratory Instrumentation

Michael Wiebusch

Abstract

We present a minimal-component bidirectional digital interconnect that enables simultaneous transmission and reception of baseband logic signals over a single coaxial cable. The circuit consists of a passive resistive hybrid providing matched line termination and directional separation, a single CMOS logic gate as driver, and a commercial LVDS receiver used as a differential comparator. No active echo cancellation, calibration, or transformer coupling is required. An analytical treatment of the hybrid network is used to determine the system parameter that maximizes the received signal amplitude. SPICE simulations predict deterministic timing errors caused by incomplete separation of transmitted and received signals. Experimental measurements confirm the predicted deterministic jitter and show good agreement with the simulation results. For typical laboratory coaxial cables up to 6 m, the measured peak-to-peak edge timing error remains below 1 ns. A bidirectional transmission experiment with randomized data at 250 MBaud demonstrates a clearly open eye diagram and confirms reliable full-duplex operation. Due to its simplicity and compatibility with existing coaxial infrastructure, the proposed approach may be useful in laboratory and detector environments where cable routing or feedthrough density is constrained.

A Minimal-Component 100 MHz Full-Duplex Digital Link Over a Single Coaxial Cable for Laboratory Instrumentation

Abstract

We present a minimal-component bidirectional digital interconnect that enables simultaneous transmission and reception of baseband logic signals over a single coaxial cable. The circuit consists of a passive resistive hybrid providing matched line termination and directional separation, a single CMOS logic gate as driver, and a commercial LVDS receiver used as a differential comparator. No active echo cancellation, calibration, or transformer coupling is required. An analytical treatment of the hybrid network is used to determine the system parameter that maximizes the received signal amplitude. SPICE simulations predict deterministic timing errors caused by incomplete separation of transmitted and received signals. Experimental measurements confirm the predicted deterministic jitter and show good agreement with the simulation results. For typical laboratory coaxial cables up to 6 m, the measured peak-to-peak edge timing error remains below 1 ns. A bidirectional transmission experiment with randomized data at 250 MBaud demonstrates a clearly open eye diagram and confirms reliable full-duplex operation. Due to its simplicity and compatibility with existing coaxial infrastructure, the proposed approach may be useful in laboratory and detector environments where cable routing or feedthrough density is constrained.
Paper Structure (7 sections, 7 equations, 10 figures)

This paper contains 7 sections, 7 equations, 10 figures.

Table of Contents

  1. Introduction
  2. Principle of Operation
  3. Circuit Implementation
  4. SPICE Simulation
  5. Experimental Results
  6. Conclusion
  7. Methods

Figures (10)

  • Figure 1: Circuit example of a directional bridge hybrid. The output of the difference amplifier suppresses the forward (L$\rightarrow$R) signal but outputs the reverse/reflected component from the far side of the transmission line. The bridge is matched to $50Ω$ and terminates the line.
  • Figure 2: Conceptual diagram of two identical transceivers connected by a single $50Ω$ cable, forming a full-duplex link. Each unit combines a driver, a resistive hybrid providing directional separation, and an LVDS receiver for recovering and redriving the signal.
  • Figure 3: Circuit diagram of one bidirectional transceiver. A CMOS logic gate (U1) drives the coaxial line through a resistive hybrid that provides $50Ω$ termination while attenuating the signal by $-4.77dB$. The resistor network simultaneously performs directional separation and DC biasing for the LVDS receiver (U2), which is operated as a high-speed differential comparator.
  • Figure 4: SPICE model of one transceiver used for simulation. The CMOS driver is represented by a pulsed voltage source with finite series resistance, the LVDS receiver is modeled as an ideal differential probe but with realistic IC pin capacitance. A lossless $50Ω$ transmission line (9 ns delay) connects to an identical remote transceiver.
  • Figure 5: Simulated full-duplex operation of two transceivers connected by a $50Ω$ transmission line (9 ns delay). Top and bottom panels show the driver voltages of transceivers A (100 MHz) and B (75 MHz), respectively. The middle panel displays node voltages at transceiver A: the line node (R), the divider node (LL), and their difference (R–LL), corresponding to the differential input of the LVDS receiver. Despite superposition of both channels, the differential signal remains well-defined.
  • ...and 5 more figures