Improved quantum circuits for division

Abstract

Arithmetic operations are an important component of many quantum algorithms. As such, coming up with optimized quantum circuits for these operations leads to more efficient implementations of the corresponding algorithms. In this paper, we develop new fault-tolerant quantum circuits for various integer division algorithms (both reversible and non-reversible). These circuits, when implemented in the Clifford+T gate set, achieve an up to 76.08\% and 68.35\% reduction in T-count and CNOT-count, respectively, compared to previous circuit constructions. Some of our circuits also improve the asymptotic T-depth from $O(n^2)$ to $O(n \log n),$ where $n$ is the bit-length of the dividend. The qubit counts are also lower than in previous works. We achieve this by expressing the division algorithms in terms of a primitive we call COMP-N-SUB, that compares two integers and conditionally subtracts them. We show that this primitive can be implemented at a cost, in terms of both Clifford and non-Clifford gates, that is comparable to one addition. This is in contrast to performing comparison and conditional subtraction separately, whose cost would be comparable to a controlled addition plus a regular addition.

Figures (9)

• Figure 1: (a) Circuit representation of a Toffoli gate. (b) A Clifford+T circuit for a Toffoli gate.
• Figure 2: (a) Circuit representation for a temporary logical AND gate. (b) A Clifford+T circuit implementation of a temporary logical AND. (c) Circuit representation for uncomputation of logical AND. (d) A circuit implementation for the uncomputation of logical AND.
• Figure 3: COMP-N-SUB circuit-I for 5-bit integers. The state of the registers $B$ and $A$ are initialized to $\ket{b}$ and $\ket{a}$, respectively. The first layer of X gates compute $\ket{\overline{b}}$. The boxed part of the circuit computes the high-bit in register $Z$. If $Z=\ket{0}$, then in the remaining part of the circuit $b-a$ is computed in register $B$. Otherwise, both registers are restored to their initial states.
• Figure 4: (a) COMP-N-SUB circuit-IIa for 5-bit integers. The first part of the circuit, up to and including unitary $U_1,$ computes the high-bit in register $Z_4$. The remaining circuit computes $b-a$ in register $B$ if $Z_4 = \ket{0}$. Otherwise, registers $B$ and $A$ are restored to their initial states of $\ket{b}$ and $\ket{a}$, respectively. (b) Quantum circuit for unitary $U_1$. (c) Quantum circuit for unitary $U_2$.
• Figure 5: COMP-N-SUB circuit-III for 5-bit integers. The boxed part of the circuit computes the high-bit in qubit $Z_4$. If $Z_4 = \ket{0}$, then the remaining part of the circuit computes the difference $b-a$ in register $B$. Otherwise, the registers $B$ and $A$ are restored to their initial states of $\ket{b}$ and $\ket{a}$, respectively.

Theorems & Definitions (1)

• Remark 3.1