Variational Phasor Circuits for Phase-Native Brain-Computer Interface Classification

Abstract

We present the \textbf{Variational Phasor Circuit (VPC)}, a deterministic classical learning architecture operating on the continuous $S^1$ unit circle manifold. Inspired by variational quantum circuits, VPC replaces dense real-valued weight matrices with trainable phase shifts, local unitary mixing, and structured interference in the ambient complex space. This phase-native design provides a unified method for both binary and multi-class classification of spatially distributed signals. A single VPC block supports compact phase-based decision boundaries, while stacked VPC compositions extend the model to deeper circuits through inter-block pull-back normalization. Using synthetic brain-computer interface benchmarks, we show that VPC can decode difficult mental-state classification tasks with competitive accuracy and substantially fewer trainable parameters than standard Euclidean baselines. These results position unit-circle phase interference as a practical and mathematically principled alternative to dense neural computation, and motivate VPC as both a standalone classifier and a front-end encoding layer for future hybrid phasor-quantum systems.

Figures (5)

• Figure 1: Single-stack Variational Phasor Circuit (VPC) schematic demonstrating consecutive shift--mix topologies. All interior shifts ($\theta$) represent pure trainable parameters; the phase-domain data encoding occurs entirely outside the bounds of the VPC block.
• Figure 2: Deep-stack VPC schematic where each block is separated by pull-back normalization for stable depth scaling.
• Figure 3: Experimental workflow used in VPC training and evaluation, from raw data preprocessing to phasor inference and gradient-based parameter updates. Phase encoding lifts each channel snapshot onto $\mathbb{T}^N$; the VPC block sequence $(S\to M \to \mathcal{P})^L$ applies trainable shift layers, local beam-splitter mixing, and pull-back normalization before readout.
• Figure 4: Binary Optimization of the Variational Phasor Circuit ($N=32$). (A) Phase-space topological representation of distinct synthetic BCI states (0: Calm, 1: Engaged) linearly mapped onto $\mathbb{T}^{32}$. (B) Convergence of the Mean Squared Error (MSE) training and validation loss curves, driven by PyTorch's Autograd against the exact analytic simulator. (C) Validation Confusion Matrix illustrating perfect partitioning of the state classes after optimization.
• Figure 5: Multi-Class BCI Optimization Matrix ($N=32$, $K=4$). (A) Spatial topologies of the 4 simulated mental states on $\mathbb{T}^{32}$. (B) Continuous Adam optimization of the 4-class Categorical Cross-Entropy loss for over 100 epochs, comparing training and validation loss performance. (C) Validation Confusion Matrix illustrating high Top-1 target confidence across distinct structural motor/flow topologies on $\mathbb{T}^{32}$.

Theorems & Definitions (6)

• Definition 2.1: VPC State Manifold
• Definition 2.2: Ambient Complex Extension
• Proposition 2.1: Unitary Mixing Extends VPC States into $\mathbb{C}^N$
• Theorem 2.1: Pull-Back Stabilization for Deep VPC Cascades
• Proposition 2.2: Linear Parameter Footprint of Deep VPC
• Corollary 2.2: Efficiency Regime of Deep-Stack VPC