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An FPGA-Based SoC Architecture with a RISC-V Controller for Energy-Efficient Temporal-Coding Spiking Neural Networks

Mohammad Javad Sekonji, Ali Mahani, Maryam Mirsadeghi, Mahdi Taheri

Abstract

Spiking Neural Networks (SNNs) offer high energy efficiency and event-driven computation, ideal for low-power edge AI. Their hardware implementation on FPGAs, however, faces challenges due to heavy computation, large memory use, and limited flexibility. This paper proposes a compact System-on-Chip (SoC) architecture for temporal-coding SNNs, integrating a RISC-V controller with an event-driven SNN core. It replaces multipliers with bitwise operations using binarized weights, includes a spike-time sorter for active spikes, and skips noninformative events to reduce computation. The architecture runs fully on a Xilinx Artix-7 FPGA, achieving up to 16x memory reduction for weights and lowering computational overhead and latency, with 97.0% accuracy on MNIST and 88.3% on FashionMNIST. This self-contained design provides an efficient, scalable platform for real-time neuromorphic inference at the edge.

An FPGA-Based SoC Architecture with a RISC-V Controller for Energy-Efficient Temporal-Coding Spiking Neural Networks

Abstract

Spiking Neural Networks (SNNs) offer high energy efficiency and event-driven computation, ideal for low-power edge AI. Their hardware implementation on FPGAs, however, faces challenges due to heavy computation, large memory use, and limited flexibility. This paper proposes a compact System-on-Chip (SoC) architecture for temporal-coding SNNs, integrating a RISC-V controller with an event-driven SNN core. It replaces multipliers with bitwise operations using binarized weights, includes a spike-time sorter for active spikes, and skips noninformative events to reduce computation. The architecture runs fully on a Xilinx Artix-7 FPGA, achieving up to 16x memory reduction for weights and lowering computational overhead and latency, with 97.0% accuracy on MNIST and 88.3% on FashionMNIST. This self-contained design provides an efficient, scalable platform for real-time neuromorphic inference at the edge.
Paper Structure (12 sections, 1 equation, 4 figures, 3 tables)

This paper contains 12 sections, 1 equation, 4 figures, 3 tables.

Table of Contents

  1. Introduction
  2. Proposed Hardware Architecture
  3. System Overview and RISC-V Controller
  4. Encoding and Spike Generation
  5. Data Flow and Pipeline Processing
  6. Flexibility and Adaptability to Non-Binary Models
  7. Optimization and Efficiency
  8. Experimental Setup and Evaluation on Hardware
  9. Performance Metrics and Analysis
  10. Flexibility and Non-Binary Model Support
  11. Hardware Optimization: BS4NN vs. S4NN
  12. Conclusion

Figures (4)

  • Figure 1: Proposed SNN hardware architecture, integrating a RISC-V controller (upper section) and a dedicated SNN processing core (lower section) with labeled components.
  • Figure 2: Proposed SNN computational flow: (I) Spike sorting and event selection; (II) Binary-weight accumulation; (III) Synaptic current calculation; (IV) Neuron integration and firing; (V) Output decoding and classification.
  • Figure 3: Power consumption breakdown of architecture.
  • Figure 4: Latency breakdown of pipeline stages.