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General circuit compilation protocol into partially fault-tolerant quantum computing architecture

Tomochika Kurita

Abstract

As we are entering an early-FTQC era, circuit execution protocols with logical qubits and certain error-correcting codes are being discussed. Here, we propose a circuit execution protocol for the space-time efficient analog rotation (STAR) architecture. Gate operations within the STAR architecture is based on lattice surgery with surface codes, but it allows direct execution of continuous gates $Rz(θ)$ as non-Clifford gates instead of $T = Rz(π/4)$. $Rz(θ)$ operations involve creation of resource states $|m_θ\rangle = \frac{1}{\sqrt{2}} (|0 \rangle + e^{iθ} |1\rangle ) $ followed by ZZ joint measurements with target logical qubits. While employing $Rz(θ)$ enables more efficient circuit execution, both their creations and joint measurements are probabilistic processes and adopt repeat-until-success (RUS) protocols which are likely to result in considerable time overhead. Our circuit execution protocol aims to reduce such time overhead by parallel trials of resource state creations and more frequent trials of joint measurements. By employing quadratic unconstrained binary optimization (QUBO) in determining resource state allocations within the space, we successfully make our protocol efficient. Furthermore, we proposed performance estimators given the target circuit and qubit topology. It successfully predicts the time performance within less time than actual simulations do, and helps find the optimal qubit topology to run the target circuits efficiently.

General circuit compilation protocol into partially fault-tolerant quantum computing architecture

Abstract

As we are entering an early-FTQC era, circuit execution protocols with logical qubits and certain error-correcting codes are being discussed. Here, we propose a circuit execution protocol for the space-time efficient analog rotation (STAR) architecture. Gate operations within the STAR architecture is based on lattice surgery with surface codes, but it allows direct execution of continuous gates as non-Clifford gates instead of . operations involve creation of resource states followed by ZZ joint measurements with target logical qubits. While employing enables more efficient circuit execution, both their creations and joint measurements are probabilistic processes and adopt repeat-until-success (RUS) protocols which are likely to result in considerable time overhead. Our circuit execution protocol aims to reduce such time overhead by parallel trials of resource state creations and more frequent trials of joint measurements. By employing quadratic unconstrained binary optimization (QUBO) in determining resource state allocations within the space, we successfully make our protocol efficient. Furthermore, we proposed performance estimators given the target circuit and qubit topology. It successfully predicts the time performance within less time than actual simulations do, and helps find the optimal qubit topology to run the target circuits efficiently.
Paper Structure (11 sections, 11 equations, 10 figures, 3 tables, 5 algorithms)

This paper contains 11 sections, 11 equations, 10 figures, 3 tables, 5 algorithms.

Figures (10)

  • Figure 1: Description of quantum operation in surface code. (a) Description of a logical qubit in surface code. The code distance is $d=5$ in this figure. A logical qubit is described as one qubit "patch". Here, blue solid (red dashed) edges of the patch denotes the physical qubit array for Pauli-Z (Pauli-X) logical operations. (b,c) Schematic description of a $Z\otimes Z$ ($X\otimes Z$) joint measurement of a logical qubit $q$ and an ancilla qubit $a$. Such measurement is executed when the two qubits are adjacent across a Z-edge (an X-edge) of the data qubit and a Z-edge of the ancilla qubit, and by measuring the joint Pauli terms of Z (X) for the edge physical qubits of the logical data qubits and Z for the ones of the logical ancilla qubits. (d) Movement of logical qubits can be done by logical qubit expansion followed by its shrinkage. (e) A $\mathsf{CNOT}$ between two logical data qubits $q_c, q_t$ can be done with a logical ancilla qubit $a$ with its state of $|+\rangle$. First, $Z \otimes Z$ joint measurement of $q_c$ and $a$ is executed, then $X \otimes X$ joint measurement of $q_c$ and $a$.
  • Figure 2: Scheme of resource state ($| m_\theta \rangle$) creation, proposed in STAR_ay1
  • Figure 3: Scheme of analog rotation $R_P(\theta)$ with a resource state $| m_\theta \rangle$, where $P$ denotes the Pauli basis of the analog rotation. The rotation $R_P(+\theta)$ becomes successful if the measurement outcome of $M_{P \otimes {\mathrm{Z}}}$ is $+1$, and $R_P(-\theta)$ acts if the outcome is $-1$.
  • Figure 4: Grid graph representing qubit spaces. Here every logical qubit is put so that the X-edges are on the left and right sides and the Z edges are on the top and bottom sides. (a) For $\mathrm{Z}\otimes P$ joint measurement with a data qubit placed in $(m,n)$, an ancilla state is placed in $(m,n \pm 1)$. (b) Similarly, for $\mathrm{X}\otimes P$ joint measurement with a data qubit placed in $(m,n)$, an ancilla state is placed in $(m\pm 1,n )$. (c,t) To perform CNOT between two data qubits, we create an ancilla state of $|+\rangle$ which connects to a Z-edge of the control qubit via and its Z-edge, and to an X-edge of the target quibit via its X-edge. The spots denoted with darkgray are the candidate positions of ancilla qubits.
  • Figure 5: Schematic description of frequent attempts of analog rotations with an example of $\mathrm{Rz}(\theta)$ operation acting on qubit $q_0$. For instance, During the first trial of an analog rotation with $|m_\theta \rangle$ on the upper Z-edge of qubit $q_0$, we can prepare for the next rotation trial, by putting the resource state $| m_{2\theta} \rangle$ on the lower Z-edge of $q_0$.
  • ...and 5 more figures