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SYMDIREC: A Neuro-Symbolic Divide-Retrieve-Conquer Framework for Enhanced RTL Synthesis and Summarization

Prashanth Vijayaraghavan, Apoorva Nitsure, Luyao Shi, Charles Mackin, Ashutosh Jadhav, David Beymer, Ehsan Degan, Vandana Mukherjee

Abstract

Register-Transfer Level (RTL) synthesis and summarization are central to hardware design automation but remain challenging for Large Language Models (LLMs) due to rigid HDL syntax, limited supervision, and weak alignment with natural language. Existing prompting and retrieval-augmented generation (RAG) methods have not incorporated symbolic planning, limiting their structural precision. We introduce SYMDIREC, a neuro-symbolic framework that decomposes RTL tasks into symbolic subgoals, retrieves relevant code via a fine-tuned retriever, and assembles verified outputs through LLM reasoning. Supporting both Verilog and VHDL without LLM fine-tuning, SYMDIREC achieves ~20% higher Pass@1 rates for synthesis and 15-20% ROUGE-L improvements for summarization over prompting and RAG baselines, demonstrating the benefits of symbolic guidance in RTL tasks.

SYMDIREC: A Neuro-Symbolic Divide-Retrieve-Conquer Framework for Enhanced RTL Synthesis and Summarization

Abstract

Register-Transfer Level (RTL) synthesis and summarization are central to hardware design automation but remain challenging for Large Language Models (LLMs) due to rigid HDL syntax, limited supervision, and weak alignment with natural language. Existing prompting and retrieval-augmented generation (RAG) methods have not incorporated symbolic planning, limiting their structural precision. We introduce SYMDIREC, a neuro-symbolic framework that decomposes RTL tasks into symbolic subgoals, retrieves relevant code via a fine-tuned retriever, and assembles verified outputs through LLM reasoning. Supporting both Verilog and VHDL without LLM fine-tuning, SYMDIREC achieves ~20% higher Pass@1 rates for synthesis and 15-20% ROUGE-L improvements for summarization over prompting and RAG baselines, demonstrating the benefits of symbolic guidance in RTL tasks.
Paper Structure (37 sections, 5 equations, 4 figures, 4 tables)

This paper contains 37 sections, 5 equations, 4 figures, 4 tables.

Table of Contents

  1. Introduction
  2. Related Work
  3. Neuro-Symbolic Divide-Retrieve- Conquer (SymDiReC) Framework
  4. Overview
  5. Divide: Symbolic Decomposition
  6. Retrieve: Symbolic Retriever
  7. Knowledge Base
  8. Joint Retriever Architecture
  9. Training Objective
  10. Inference: Retrieving Sub-components
  11. Conquer with LLM-Guided Verification and Assembly
  12. Experiments
  13. Benchmarks and Baselines
  14. Evaluation Metrics
  15. Results & Discussion
  16. ...and 22 more sections

Figures (4)

  • Figure 1: Overview of our SymDiReC framework for RTL synthesis and summarization.
  • Figure 2: Illustration of our SymDiReC framework for 8-bit carry ripple adder.
  • Figure 3: Ablation results: Performance with varying (a) number of sub-components and (b) chunking strategy.
  • Figure 4: VHDL Samples of different transformation strategies applied using the three categories of code clones -- Type 2, Type 3 and Type 4.