Optimizing Logical Mappings for Quantum Low-Density Parity Check Codes

Abstract

Early demonstrations of fault tolerant quantum systems have paved the way for logical-level compilation. For fault-tolerant applications to succeed, execution must finish with a low total program error rate (i.e., a low program failure rate). In this work, we study a promising candidate for future fault-tolerant architectures with low spatial overhead: the Gross code. Compilation for the Gross code entails compiling to Pauli Based Computation and then reducing the rotations and measurements to the Bicycle ISA. Depending on the configuration of modules and the placement of code modules on hardware, one can reduce the amount of resulting Bicycle instructions to produce a lower overall error rate. We find that NISQ-based, and existing FTQC mappers are insufficient for mapping logical qubits on Gross code architectures because 1. they do not account for the two-level nature of the logical qubit mapping problem, which separates into code modules with distinct measurements, and 2. they naively account only for length two interactions, whereas Pauli-Products are up to length $n$, where $n$ is the number of logical qubits in the circuit. For these reasons, we introduce a two-stage pipeline that first uses hypergraph partitioning to create in-module clusters, and then executes a priority-based algorithm to efficiently assign clusters onto hardware. We find that our mapping policy reduces the error contribution from inter-module measurements, the largest source of error in the Gross Code, by up to $\sim36\%$ in the best case, with an average reduction of $\sim13\%$. On average, we reduce the failure rates from inter-module measurements by $\sim22\%$ with localized factory availability, and by $\sim17\%$ on grid architectures, allowing hardware developers to be less constrained in developing scalable fault tolerant systems due to software driven reductions in program failure rates.

Figures (19)

• Figure 1: (a) Three gross-code modules (12 qubits per module) connected linearly. Magic states are routed via inter-module connections to perform PRRs both within and across gross-code modules. (b) Qubits are initially divided into modules $\{q_0,q_1,q_2\}$ and $\{q_3,q_4,q_5\}$, requiring 4 inter-module interactions to complete the program. After re-partitioning into $\{q_0,q_3,q_5\}$ and $\{q_1,q_4,q_2\}$, the number of inter-module interactions reduces to only 1. (c) Our mapping policy compared to current state-of-the-art baselines. Dark blue modules contain qubits associated with the operation, while light blue modules are used only for routing to other modules. Either baselines perform adequate placement, but neglect routing, or vice versa, incurring substantial overhead by using more inter-module connections than required. Our mapping policy performs improved placement and routing to reduce the number of inter-module connections required to perform PPRs, significantly improving program success rate and reducing error accumulation.
• Figure 2: A schematic illustrating the compilation of a circuit into its Pauli-Based Computation (PBC) form. (a) A circuit transpiled into H, S, CX, and T (or Rz) gates. Non-Clifford gates are shown in orange, Clifford gates in green, and measurements in blue. The anticommutation rule (d) and commutation rule (e) (see Ref. litinski2019gameofsurfacecodes for details) are applied to systematically commute non-Clifford gates to the front, producing the intermediate representation in (b). Applying these rules to the measurements results in the fully translated PBC circuit in (c).
• Figure 3: Translation from a Pauli-Based Computation (PBC) circuit to the Gross-code Bicycle instruction set. (a) PBC circuit with Clifford measurements represented by blue boxes and non-Clifford measurements by orange boxes. (b) Resulting instruction sequence for execution on the Gross code, including in-module measurements (white boxes), inter-module measurements (grey boxes), and non-Clifford operations (orange boxes), the latter realized through T-state injection shown in (c). See Ref. tourdegross for further architectural details.
• Figure 4: A plot showing how SWAP insertion leads to a substantial increase in program error rate, contrary to NISQ compilation schemes. We evaluate the SABRESWAP strategy by inserting SWAPs every $f$ rotations, and vary $f$ between $25$ and $100$ rotations at intervals of $25$ rotations. Smaller $f$ leads to a much larger increase in inter-module measurements, which also makes it infeasible to simulate SABRESWAP strategies on all benchmark suites, or with a higher number of trials.
• Figure 5: A figure illustrating the effect of logical-qubit remapping on in-module measurement cost. Left: A naive mapping leads to higher cost. Right: A mapping exploiting the in-module measurement Clifford table leads to significantly reduced cost.