Logo
ScienceStack
Table of Contents
Fetching ...
Sign In

ETM2: Empowering Traditional Memory Bandwidth Regulation using ETM

Alexander Zuepke, Ashutosh Pradhan, Daniele Ottaviano, Andrea Bastoni, Marco Caccamo

Abstract

The Embedded Trace Macrocell (ETM) is a standard component of Arm's CoreSight architecture, present in a wide range of platforms and primarily designed for tracing and debugging. In this work, we demonstrate that it can be repurposed to implement a novel hardware-assisted memory bandwidth regulator, providing a portable and effective solution to mitigate memory interference in real-time multicore systems. ETM2 requires minimal software intervention and bridges the gap between the fine-grained microsecond resolution of MemPol and the portability and reaction time of interrupt-based solutions, such as MemGuard. We assess the effectiveness and portability of our design with an evaluation on a large number of 64-bit Arm boards, and we compare ETM2 with previous works using a setup based on the San Diego Vision Benchmark Suite on the AMD Zynq UltraScale+. Our results show the scalability of the approach and highlight the design trade-offs it enables. ETM2 is effective in enforcing per-core memory bandwidth regulation and unlocks new regulation options that were infeasible under MemGuard and MemPol.

ETM2: Empowering Traditional Memory Bandwidth Regulation using ETM

Abstract

The Embedded Trace Macrocell (ETM) is a standard component of Arm's CoreSight architecture, present in a wide range of platforms and primarily designed for tracing and debugging. In this work, we demonstrate that it can be repurposed to implement a novel hardware-assisted memory bandwidth regulator, providing a portable and effective solution to mitigate memory interference in real-time multicore systems. ETM2 requires minimal software intervention and bridges the gap between the fine-grained microsecond resolution of MemPol and the portability and reaction time of interrupt-based solutions, such as MemGuard. We assess the effectiveness and portability of our design with an evaluation on a large number of 64-bit Arm boards, and we compare ETM2 with previous works using a setup based on the San Diego Vision Benchmark Suite on the AMD Zynq UltraScale+. Our results show the scalability of the approach and highlight the design trade-offs it enables. ETM2 is effective in enforcing per-core memory bandwidth regulation and unlocks new regulation options that were infeasible under MemGuard and MemPol.
Paper Structure (30 sections, 10 equations, 23 figures, 2 tables)

This paper contains 30 sections, 10 equations, 23 figures, 2 tables.

Table of Contents

  1. Introduction
  2. Background and Related Work
  3. MemGuard
  4. MemPol
  5. Regulation Granularity
  6. Arm CoreSight
  7. ETM Background
  8. Design
  9. External Inputs to the ETM
  10. Counters
  11. External Outputs of the ETM
  12. Sequencer
  13. Periodic Replenishment (PR) Regulation
  14. Token Bucket (TB) Regulation
  15. Address-based Regulation (PR-user)
  16. ...and 15 more sections

Figures (23)

  • Figure 1: High-level comparison among traditional memory bandwidth regulation mechanisms MemGuard and MemPol, and the presented ETM2. High-lighted in green is the regulation logic. Lightning arrows indicate interrupts.
  • Figure 2: Arm CoreSight components, highlighting the modules used by ETM2.
  • Figure 3: Internal ETM architecture, highlighting the modules used by ETM2.
  • Figure 4: ETM2 PR regulation: The design follows MemGuard by using two counters for budget accounting and periodic replenishment. The sequencer turns the counter transitions (edge) into stable output signals (level). State 3 indicates throttling to the OS or Hypervisor via CTIIRQ.
  • Figure 5: ETM2 TB regulation: The design follows MemPol's token-bucket approach with the two counters driving the state machine transitions back and forth. Depending on the TB variant, states 1 to 3 indicate throttling. ETM2 TB 2:2 provides robustness for both small and large regulation budgets.
  • ...and 18 more figures