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A Novel Approach for Fault Detection and Failure Analysis of CMOS Copper Metal Stacks

Gregor Hieronymus Eberwein, Gianluca Aglieri Rinella, Daniela Bortoletto, Szymon Bugiel, Francesca Carnesecchi, Antonello Di Mauro, Pedro Vicente Leitao, Hartmut Hillemanns, Marc Alain Imhoff, Antoine Junique, Alex Kluge, Magnus Mager, Paolo Martinengo, Iaroslav Panasenko, Ivan Ravasenga, Felix Reidt, Valerio Sarritzu, Walter Snoeys, Miljenko Šuljić

Abstract

For the Inner Tracking System 3 (ITS3) upgrade, the ALICE experiment at CERN requires monolithic active pixel sensors of dimensions up to 97~mm$\,\times\,$266~mm, occupying a large fraction of a 300 mm wafer. To manufacture such a wafer-scale device, larger than the single design reticle size, stitching is employed. The MOnolithic Stitched Sensor (MOSS) is a prototype silicon pixel sensor of 14~mm$\,\times\,$259~mm size with the primary goal of understanding the stitching technique and yield. Given the large size, high yield is paramount for the ITS3 sensors, and an in-depth yield characterization was performed on these MOSS sensors. In a collaborative effort, the foundry adapted the metal stack to the requirements of the project, but recurrent fault signatures were discovered with various frequencies across all 20 wafers tested, and correlated through dedicated measurements and analyses. Following these findings, the foundry implemented a mitigation strategy to avoid the issue in the future. This article does not describe process details but concentrates on the measurements and analysis method.

A Novel Approach for Fault Detection and Failure Analysis of CMOS Copper Metal Stacks

Abstract

For the Inner Tracking System 3 (ITS3) upgrade, the ALICE experiment at CERN requires monolithic active pixel sensors of dimensions up to 97~mm266~mm, occupying a large fraction of a 300 mm wafer. To manufacture such a wafer-scale device, larger than the single design reticle size, stitching is employed. The MOnolithic Stitched Sensor (MOSS) is a prototype silicon pixel sensor of 14~mm259~mm size with the primary goal of understanding the stitching technique and yield. Given the large size, high yield is paramount for the ITS3 sensors, and an in-depth yield characterization was performed on these MOSS sensors. In a collaborative effort, the foundry adapted the metal stack to the requirements of the project, but recurrent fault signatures were discovered with various frequencies across all 20 wafers tested, and correlated through dedicated measurements and analyses. Following these findings, the foundry implemented a mitigation strategy to avoid the issue in the future. This article does not describe process details but concentrates on the measurements and analysis method.
Paper Structure (14 sections, 12 figures, 3 tables)

This paper contains 14 sections, 12 figures, 3 tables.

Table of Contents

  1. Introduction
  2. MOSS prototype sensor
  3. Measurement techniques
  4. Impedance measurement
  5. Powering setup with thermal camera
  6. Chip design correlation
  7. Data analysis
  8. Impedance measurement
  9. Power ramping and hotspot location distribution
  10. Hypothesis formation
  11. Hypothesis validation and implications
  12. Cross-section imaging
  13. Mitigation and future testing
  14. Conclusion

Figures (12)

  • Figure 1: Schematic structure of the MOSS sensor.
  • Figure 2: MOSS sensor (center) mounted on the testing PCB (green), with the protective cover removed. A breakout board (red) in impedance measurement configuration is connected to the top left high-density connector. The dimensions of the testing PCB are 150 mm$\,\times\,$350 mm.
  • Figure 3: Power net pair succeeding (a), and classified as short (b) in the impedance measurement.
  • Figure 4: Example of power ramp turn-on curves. The plot on the left shows a burn-through during the ramp-up of the AVDD power net. After the burn-through, the turn-on curves follow the standard behavior of a MOSS chip. The legend entries correspond to the power domains in Table \ref{['tab:power_nets']}.
  • Figure 5: Thermal camera image analysis steps. (a) The HU under test prior to powering with marked fiducials and ROI. (b) The hotspot candidate image. (c) The difference between (a) and (b). (d) The final denoised image used to extract the hotspot location. Insets in (b), (c), (d) illustrate the extracted location. The black circle has a radius of 5 pixels, centered on the hotspot location.
  • ...and 7 more figures