A Scalable Open-Source QEC System with Sub-Microsecond Decoding-Feedback Latency

Abstract

Quantum error correction (QEC) is essential for realizing large-scale, fault-tolerant quantum computation, yet its practical implementation remains a major engineering challenge. In particular, QEC demands precise real-time control of a large number of qubits and low-latency, high-throughput and accurate decoding of error syndromes. While most prior work has focused primarily on decoder design, the overall performance of any QEC system depends critically on all its subsystems including control, communication, and decoding, as well as their integration. To address this challenge, we present an open-source, fully integrated QEC system built on RISC-Q, a generator for RISC-V-based quantum control architectures. Implemented on RFSoC FPGAs, our system prototype integrates real-time qubit control, a scalable distributed multi-board architecture, and the state-of-the-art hardware QEC decoder within a low-latency, high-throughput decoding pipeline, forming a complete hardware platform ready for deployment with superconducting qubits. Experimental evaluation on a three-board prototype based on AMD ZCU216 RFSoCs demonstrates an end-to-end QEC decoding-feedback latency of 446 ns for a distance-3 surface code, including syndrome aggregation, network communication, syndrome decoding, and error distribution. Extrapolating from measured subsystem performance and state-of-the-art decoder benchmarks, the architecture can achieve sub-microsecond decoding-feedback latency up to a distance-21 surface code ($\sim$881 physical qubits) when scaled to larger hardware configurations.

Figures (10)

• Figure 1: The tree topology of the distributed architecture. The leaf nodes are connected to the physical qubits and process RF signals for controlling qubits. The root node hosts the QEC decoder that decodes syndromes in real-time. The system is extensible by introducing more router nodes.
• Figure 2: A typical setup of a 14-qubit control system on a AMD ZCU216 RFSoC. Each qubit has a dedicated RISC-V controller, associated with a DAC channel (DAC1-7 and DAC9-15) for gate operation. Besides, the qubits are grouped in 7, where all qubits in a group share a DAC channel (DAC8 and DAC16) for measurement.
• Figure 3: Controller Core: A Schematic Overview
• Figure 4: Software stack of the QEC system. Hardware modules are generated in SpinalHDL and synthesized into a bitstream, while control programs are compiled into RISC-V binaries using the standard RISC-V LLVM toolchain. Both artifacts are delivered from the host to the RFSoC over Ethernet via an HTTP interface, where an HTTP server on ARM loads them onto the FPGA fabric.
• Figure 5: FPGA floorplan of a leaf-node implementation on the AMD ZCU216 RFSoC. Yellow areas correspond to RISC-V controller cores, green areas to RF signal decoders, and purple areas to RF signal generators.