Evaluating Four FPGA-accelerated Space Use Cases based on Neural Network Algorithms for On-board Inference

Abstract

Space missions increasingly deploy high-fidelity sensors that produce data volumes exceeding onboard buffering and downlink capacity. This work evaluates FPGA acceleration of neural networks (NNs) across four space use cases on the AMD ZCU104 board. We use Vitis AI (AMD DPU) and Vitis HLS to implement inference, quantify throughput and energy, and expose toolchain and architectural constraints relevant to deployment. Vitis AI achieves up to 34.16$\times$ higher inference rate than the embedded ARM CPU baseline, while custom HLS designs reach up to 5.4$\times$ speedup and add support for operators (e.g., sigmoids, 3D layers) absent in the DPU. For these implementations, measured MPSoC inference power spans 1.5-6.75 W, reducing energy per inference versus CPU execution in all use cases. These results show that NN FPGA acceleration can enable onboard filtering, compression, and event detection, easing downlink pressure in future missions.

Figures (13)

• Figure 1: Example input to the VAE model: a cropped image of a solar active region showing the radial component of the Sun’s magnetic field. White areas indicate outward (positive) magnetic flux, and black areas indicate inward (negative) flux. The bright region near the center corresponds to a sunspot with strong positive polarity, surrounded by weaker areas of opposite polarity.
• Figure 2: VAE encoder architecture (sampling and exponent handled on CPU).
• Figure 3: CNetPlusScalar architecture after replacing leaky ReLU with ReLU.
• Figure 4: Parallel multi-ESPERTA architecture (six shared-input models).
• Figure 5: BaselineNet architecture.