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Retrieve, Schedule, Reflect: LLM Agents for Chip QoR Optimization

Yikang ouyang, Yang Luo, Dongsheng Zuo, Yuzhe Ma

Abstract

Modern chip design requires multi-objective optimization of timing, power, and area under stringent time-to-market constraints. Although powerful optimization algorithms are integrated into EDA tools, achieving high QoR hinges on effective long-horizon scheduling, which relies heavily on manual expert intervention. To address this issue and automate chip design, we propose an agentic LLM framework that schedules chip optimizations through direct interaction with EDA tools. The agent is grounded in natural language expertise expressed as a search tree through retrieval-augmented generation (RAG). We further improve scheduling quality with Pareto-driven QoR feedback through language reflection. Experimental results show that, compared with black-box search methods such as reinforcement learning, our framework achieves 10% greater timing improvement while consuming less power and area, with more than 4x speedup. The post-optimization QoR is also comparable to that achieved by human experts. Finally, the agent supports customized tasks expressed in natural language, enabling preferential QoR trade-offs. The code and chip design data will be publicly available at https://github.com/YiKangOY/Open-LLM-ECO.

Retrieve, Schedule, Reflect: LLM Agents for Chip QoR Optimization

Abstract

Modern chip design requires multi-objective optimization of timing, power, and area under stringent time-to-market constraints. Although powerful optimization algorithms are integrated into EDA tools, achieving high QoR hinges on effective long-horizon scheduling, which relies heavily on manual expert intervention. To address this issue and automate chip design, we propose an agentic LLM framework that schedules chip optimizations through direct interaction with EDA tools. The agent is grounded in natural language expertise expressed as a search tree through retrieval-augmented generation (RAG). We further improve scheduling quality with Pareto-driven QoR feedback through language reflection. Experimental results show that, compared with black-box search methods such as reinforcement learning, our framework achieves 10% greater timing improvement while consuming less power and area, with more than 4x speedup. The post-optimization QoR is also comparable to that achieved by human experts. Finally, the agent supports customized tasks expressed in natural language, enabling preferential QoR trade-offs. The code and chip design data will be publicly available at https://github.com/YiKangOY/Open-LLM-ECO.
Paper Structure (31 sections, 12 equations, 5 figures, 8 tables, 1 algorithm)

This paper contains 31 sections, 12 equations, 5 figures, 8 tables, 1 algorithm.

Table of Contents

  1. Introduction
  2. Preliminaries
  3. Chip Optimization
  4. LLM for Chip Optimization
  5. LLM for Task Scheduling
  6. Problem Formulation
  7. Search Tree–based Retrieval-augmented Scheduling
  8. Search Tree Representation and Knowledge Store
  9. Path-based RAG
  10. Agentic Schedule--Execute--Reflect Framework
  11. Within-round Schedule--Execute Loop
  12. Across-round Pareto-driven Reflection
  13. Filtering Pareto-optimal Traces
  14. Scheduler/Executor Two-level Reflection
  15. Experimental Results
  16. ...and 16 more sections

Figures (5)

  • Figure 1: Chip QoR optimization as an iterative schedule--execute--reflect workflow.
  • Figure 2: Scheduling strategy constructed as a search tree and path-based RAG.
  • Figure 3: Overview of our framework. (a) Rounds of chip optimization scheduling. (b) Iterative retrieve-schedule-reflect with execution with in one round. (c) Example prompt and agent response snippets.
  • Figure 4: QoR trend within the last scheduled optimization round of "mempool tile_wrap" design.
  • Figure 5: Runtime breakdown for NVDLA_partition_m and hidden1. Each pie chart shows the percentage of total runtime spent in LLM interaction and EDA tool. The Other section denotes other runtime costs like loading chip designs into EDA tools.