Phononic Bragg Reflectors for Thermal Insulation of Scalable Cryogenic Control Electronics from Qubits

Abstract

Scaling solid-state architectures to the millions of qubits required for utility-scale quantum computing could benefit from the integration of control electronics in the immediate vicinity of the quantum layer. However, lithographically fabricated solid-state qubits perform best at temperatures well below 1 K, where available cooling power is limited, whereas the control electronics dissipate substantial power and therefore require the higher cooling power available at elevated temperatures. To address this challenge, we propose a cryopackaging concept that uses broadband phononic Distributed Bragg Reflectors (DBRs) as a thermal barrier between cryoelectronics and the qubit chip. As an experimental realization of this concept, we fabricate and characterize Ta/SiO$_2$ DBR structures. In this architecture, the DBR is intended to provide mechanical support for superconducting vias while offering substantially better thermal insulation than typical bulk materials. For a 600-nm-thick DBR consisting of 10 Ta/SiO$_2$ bilayers, we obtain a thermal conduction below 1 mW/cm$^2$ from 1.5 K to 100 mK. In a centimeter-scale architecture, this level of isolation is compatible with Watt-level cooling power for nearby electronics while maintaining a qubit temperature around 100 mK in commercially available dilution refrigerators.

Figures (10)

• Figure 1: Concept of cryopackaging for close-to-qubit control (not to scale). Schematic of the proposed architecture, in which the cryoelectronics chip is thermally anchored to a warmer stage with higher cooling power, while the qubit chip remains connected to the mixing chamber (MXC) stage at $100mK$. A phononic distributed Bragg reflector (DBR) stack acts as a thermal barrier between the chips while accommodating dielectric lining and superconducting (SC) through-vias for dense electrical interconnects. The DBR reflects phonons emitted by the cryoelectronics, thereby reducing heat flow toward the qubit layer. All numbers shown are design targets or estimates rather than measured values (see also Appendix \ref{['sec:Estimates_concept']}).
• Figure 2: Experimental Setup. a Overview of the three DBR sample types investigated: the total Ta/SiO2 thicknesses are $600nm$ (A), $440nm$ (B), and $109nm$ (C). In addition, three reference samples consisting of bare Si (D) and SiO2 layers of $503nm$ (E) and $1438nm$ (F) on Si substrates are measured (samples D, E, and F are described in \ref{['tab:Samples']}). Sample E serves as the bulk material reference for sample B due to its comparable thickness, while sample F is more than twice as thick as the thickest DBR (A). At least two samples were measured for each type. b Schematic of the experimental configuration. Each sample is mounted with the DBR or reference oxide facing away from the heater, on an Si interposer with a $200n m$-thin gold-coated backside. Both Si pieces are intended to homogenize the temperature laterally, so that a uniform temperature is maintained even if the heat is applied locally. The interposer is attached to a gold-plated oxygen-free high-conductivity (OFHC) copper holder that is tightly screwed onto the mixing chamber (MXC) plate of the dilution refrigerator. A $50µ m$ indium foil between the gold surfaces provides enhanced Cu–Si thermal contact. The sample is bonded to the interposer using silver epoxy, and a resistive heater is mounted on the top surface. During measurements, the heater power is varied between $0W$ and $1mW$, and temperatures are monitored on the sample, interposer, and holder ($T_{\mathrm{H}}$, $T_{\mathrm{L}}$, and $T_\mathrm{MXC}$). The MXC temperature is stabilized via a PID loop at $100mK$ to $700mK$ in steps of $100mK$.
• Figure 3: Exemplary raw data. Calibrated raw data for two samples of comparable thickness: DBR B (green) and reference E (orange, see \ref{['tab:Samples']} and \ref{['fig:Fig2_Setup_Samples']}a. Even though the applied heating power $P$ was increased from $0W$ to $1mW$ in both cases, the values of $P/A$ vary due to slight differences in sample dimensions. The data points for $P~=~0W$ are not visible because of the logarithmic axes. The different transparencies correspond to fixed mixing chamber temperatures $T_{\mathrm{MXC}}$ between $100mK$ (solid color) and $700mK$ (most transparent color). The data show that both, $T_{\mathrm{H}}$ (+) and $T_{\mathrm{L}}$ ($\bullet$), vary with increasing $P$, indicating that a self-consistent analysis is required to extract the thermal sample properties according to \ref{['eq:heat_flow']}.
• Figure 4: Iterative analysis of experimental data for sample E at $100mK$ based on \ref{['eq:heat_flow']}.a Illustration of the iterative correction procedure. Black crosses show the measured data, the blue line the initial PCHIP interpolation, pink dots the interpolated correction terms, and grey crosses with orange line the corrected data and final interpolation after 30 iterations. Measurements at seven mixing chamber temperatures between $100mK$ and $700mK$ demonstrate consistent results; curves for $T_{\mathrm{MXC}} \geq 200mK$ are shifted by constant offsets as described in the text. b Effective thermal conductivity $\lambda_{\mathrm{eff}}(T)$ obtained from the derivative of the final $I(T)$. The agreement between curves derived from different $T_{\mathrm{MXC}}$ confirms the consistency of the method.
• Figure 5: Verification of the iterative analysis method for sample E at $100mK$.a Heat integrals $I_n(T)$ obtained after successive iterations (continuous lines). In Addition, calculated values $[I_n(T_{\mathrm{H}})-I_n(T_{\mathrm{L}})]$ ($\bullet$) are compared with the measured data (+), showing good agreement for $n=30$. b Absolute deviation between the measured values and the recalculated heat flow decreases with iteration number. c Relative deviation between measurement and model. After 30 iterations (orange), the deviation falls below $2%$, indicating convergence of the method.