An Extended Study of Gear-Ratio-Aware Standard Cell Layout Generation for DTCO Exploration

Abstract

Advanced nodes decouple contacted poly pitch (CPP) and lower-metal pitch to improve routability. We present CPCell, an efficient standard-cell layout generation framework, to support arbitrary gear ratio (GR) and offset parameters through a fine-grained layered grid graph and constraint-programming-based placement-routing co-optimization. Layout quality is improved via Middle-of-Line routing, M0 pin enablement, pin accessibility constraints and a weighted multi-objective formulation that jointly optimizes cell layouts. To scale to netlists with up to 48 transistors, we incorporate acceleration techniques including transistor clustering, identical transistor partitioning, routing lower bound tightening and early termination strategies. Comprehensive cell-level and block-level studies are conducted to evaluate GR and offset choices, quantify the benefits of the proposed objectives and assess their impact on power, performance, area and IR-drop outcomes.

Figures (17)

• Figure 1: An example of M1 routing resources corresponding to different gear-ratio settings within a 7-CPP cell layout. Dummy M1 columns are used at the left-end and the right-end of the cell layout to avoid overlapping columns with adjacent cell layouts. The rest of the M1 columns are counted as available routing resources. (a) 1:1 GR. (b) 3:2 GR with its offset variant. (c) 5:3 GR with its two offset variants.
• Figure 5: Top-down view of the irregular pattern of columns on $L^2$ induced by different pitch values on $L^1$ and $L^3$.
• Figure 6: An example of routing from both source/drain and gate locations in the placement grid to the frontside IO through $L^2$, $L^3$ and $L^4$. A super cut node, $scx$, is defined on each column on the placement grid to control the flow along the middle rows. On each routing grid, interconnections are made following the layer orientation. Between each pair of layers, vias are constructed at access points (colored squares) to make connections.
• Figure 7: An example on MUX2_X1 with different minimum cut width setting (1-CPP or 2-CPP). Cut width and cut shape are abstracted by super cut nodes $scx$. (a) When 2-CPP cut width is enforced, $scx$ are grouped with adjacent columns to produce a longer cut shape. (b) When 1-CPP cut width is enforced, $scx$ can be set to True individually to produce a shorter cut shape.
• Figure 8: An example of geometric variables defined on vertices. Each vertex is paired with a set of geometric variables corresponding to four directions: left, right (see (a)), front and back (see (b)), indicating the end of a metal segment.