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SRAM-Based Compute-in-Memory Accelerator for Linear-decay Spiking Neural Networks

Hongyang Shang, Shuai Dong, Yahan Yang, Junyi Yang, Peng Zhou, Arindam Basu

Abstract

Spiking Neural Networks (SNNs) have emerged as a biologically inspired alternative to conventional deep networks, offering event-driven and energy-efficient computation. However, their throughput remains constrained by the serial update of neuron membrane states. While many hardware accelerators and Compute-in-Memory (CIM) architectures efficiently parallelize the synaptic operation (W x I) achieving O(1) complexity for matrix-vector multiplication, the subsequent state update step still requires O(N) time to refresh all neuron membrane potentials. This mismatch makes state update the dominant latency and energy bottleneck in SNN inference. To address this challenge, we propose an SRAM-based CIM for SNN with Linear Decay Leaky Integrate-and-Fire (LD-LIF) Neuron that co-optimizes algorithm and hardware. At the algorithmic level, we replace the conventional exponential membrane decay with a linear decay approximation, converting costly multiplications into simple additions while accuracy drops only around 1%. At the architectural level, we introduce an in-memory parallel update scheme that performs in-place decay directly within the SRAM array, eliminating the need for global sequential updates. Evaluated on benchmark SNN workloads, the proposed method achieves a 1.1 x to 16.7 x reduction of SOP energy consumption, while providing 15.9 x to 69 x more energy efficiency, with negligible accuracy loss relative to original decay models. This work highlights that beyond accelerating the (W x I) computation, optimizing state-update dynamics within CIM architectures is essential for scalable, low-power, and real-time neuromorphic processing.

SRAM-Based Compute-in-Memory Accelerator for Linear-decay Spiking Neural Networks

Abstract

Spiking Neural Networks (SNNs) have emerged as a biologically inspired alternative to conventional deep networks, offering event-driven and energy-efficient computation. However, their throughput remains constrained by the serial update of neuron membrane states. While many hardware accelerators and Compute-in-Memory (CIM) architectures efficiently parallelize the synaptic operation (W x I) achieving O(1) complexity for matrix-vector multiplication, the subsequent state update step still requires O(N) time to refresh all neuron membrane potentials. This mismatch makes state update the dominant latency and energy bottleneck in SNN inference. To address this challenge, we propose an SRAM-based CIM for SNN with Linear Decay Leaky Integrate-and-Fire (LD-LIF) Neuron that co-optimizes algorithm and hardware. At the algorithmic level, we replace the conventional exponential membrane decay with a linear decay approximation, converting costly multiplications into simple additions while accuracy drops only around 1%. At the architectural level, we introduce an in-memory parallel update scheme that performs in-place decay directly within the SRAM array, eliminating the need for global sequential updates. Evaluated on benchmark SNN workloads, the proposed method achieves a 1.1 x to 16.7 x reduction of SOP energy consumption, while providing 15.9 x to 69 x more energy efficiency, with negligible accuracy loss relative to original decay models. This work highlights that beyond accelerating the (W x I) computation, optimizing state-update dynamics within CIM architectures is essential for scalable, low-power, and real-time neuromorphic processing.
Paper Structure (11 sections, 4 equations, 7 figures, 1 table)

This paper contains 11 sections, 4 equations, 7 figures, 1 table.

Table of Contents

  1. Introduction
  2. Methodology
  3. Linear Decay Leaky Integrate-and-Fire (LD-LIF) Neuron
  4. Unit Cell for Membrane Potentials
  5. SNN Learning Algorithm with LD-LIF Neuron
  6. Hardware Architecture for SNN
  7. Results
  8. Algorithm Results
  9. Latency and Energy Comparisons for LD-LIF Module
  10. Comparison with Other Existing Works
  11. Conclusion

Figures (7)

  • Figure 1: Comparison between the conventional LIF model with exponential decay and the proposed LD-LIF implemented in SRAM-based CIM.
  • Figure 2: Hardware Architecture of SRAM-based In-Memory Computing with Linear Decay.
  • Figure 3: Schematic and operation of the membrane voltage cell. (a) Circuit of the membrane voltage cell. (b) Data flow for the membrane voltage update process. (c)Waveform of membrane voltage cell operation.
  • Figure 4: Performance comparison of Baseline, Linear Decay, and Quantization methods among SHD, NMNIST and DVS Gesture datasets.
  • Figure 5: The learned linear decay $\beta$ parameters among three networks: (a) MLP-1 on N-MNIST, (b) MLP-2 on SHD, and (c) CNN on DVS Gesture.
  • ...and 2 more figures