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Cold source field-effect transistor with type-III band-aligned HfS$_2$/WTe$_2$ heterostructure

Shujin Guo, Qing Shi, Deping Guo, Fei Liu, Xianghua Kong, Yonghong Zhao, Hong Guo

Abstract

The cold source field-effect transistor (CSFET) is promising for reducing power dissipation in integrated circuits by engineering the density of states at the injecting source. Existing CSFET designs utilizing Dirac-source metals or p-Metal-n stacks are challenged by Schottky barriers at the metal-semiconductor interface. In this work, a 2D WTe$_2$/HfS$_2$ heterojunction with type-III band alignment is proposed to be an excellent design of cold source and CSFET. The architecture has a high band-to-band transport mechanism by removing the detrimental Schottky barrier issues. Importantly, the proposed CSFET has the same channel barrier modulation principle as conventional MOSFET to enable a high on-state current. Using first-principles-based quantum transport modeling, we predict a very high $I_{\rm on}$/$I_{\rm off}$ ratio at $\sim$ 10$^{10}$, a low subthreshold swing below the thermal limit for a wide range of gate voltages, reaching as small as 41.3 mV/dec, at low source-drain bias $V_{DS}=0.3$ $\rm V$. These findings establish a design principles for next-generation low-power nanoelectronic switches leveraging 2D van der Waals heterostructures.

Cold source field-effect transistor with type-III band-aligned HfS$_2$/WTe$_2$ heterostructure

Abstract

The cold source field-effect transistor (CSFET) is promising for reducing power dissipation in integrated circuits by engineering the density of states at the injecting source. Existing CSFET designs utilizing Dirac-source metals or p-Metal-n stacks are challenged by Schottky barriers at the metal-semiconductor interface. In this work, a 2D WTe/HfS heterojunction with type-III band alignment is proposed to be an excellent design of cold source and CSFET. The architecture has a high band-to-band transport mechanism by removing the detrimental Schottky barrier issues. Importantly, the proposed CSFET has the same channel barrier modulation principle as conventional MOSFET to enable a high on-state current. Using first-principles-based quantum transport modeling, we predict a very high / ratio at 10, a low subthreshold swing below the thermal limit for a wide range of gate voltages, reaching as small as 41.3 mV/dec, at low source-drain bias . These findings establish a design principles for next-generation low-power nanoelectronic switches leveraging 2D van der Waals heterostructures.
Paper Structure (1 section, 2 equations, 5 figures)

This paper contains 1 section, 2 equations, 5 figures.

Table of Contents

  1. Acknowledgments

Figures (5)

  • Figure 1: (a) The crystal of WTe$_2$/HfS$_2$ vdWH from the top and side view. WTe$_2$/HfS$_2$ vdWH stacks by fcc-I stacking pattern, in which the W atom is located above the S atom, Te atom aligns with the other S atom. (b) The band structure of WTe$_2$/HfS$_2$ vdWH calculated with PBE functional. (c) The band alignment of WTe$_2$/HfS$_2$ vdWH before and after contact. (d) and (e) are the crystal structure and the band alignment of the cold source. $L_{ov}$ is the overlap length of the vdWH. Edge atoms refer to the most right atoms and the most left atoms in the overlapped region.
  • Figure 2: The on-state current of cold sources with (a) different doping concentration, (b) different edge atoms and (c) varied overlap length. (d),(e),(f) are the corresponding transmission spectrum of (a),(b) and (c). The current is calculated by integrating the transmission spectrum between the tunneling window.
  • Figure 3: The probability density of scattering states of cold sources with different edge atoms: (a) W+Hf, (b) W+S, (c) Te+Hf, (d) Te+S.
  • Figure 4: (a) The schematic diagram of the CSFET with double gates. (b) The atomic structure of the entire CSFET, in which the cold source consists of P-type WTe$_2$, WTe$_2$/HfS$_2$ vdWH and N-type HfS$_2$. (c) The band alignment of the whole CSFET.
  • Figure 5: The (a) $I_{DS}-V_G$ curve and (b) corresponding SS of CSFET with $V_{DS}$ = 0.3 V. (c) and (d) are the local density of states (LDOS) of CSFET at off-state ($V_G$ = 0 V) and on-state ($V_G$ = 0.7 V). (e) The projected local density of states (PLDOS) of Source-1, vdWH, Source-2, channel and drain, and transmission spectrum at off-state and on-state. Tr. is the abbreviation of transmission.