Scalable DNA Ternary Full Adder Enabled by a Competitive Blocking Circuit

Abstract

DNA adder circuits are programmable reaction networks that process DNA molecular inputs to compute a sum and serve as essential components for digital computation. Currently, DNA adders primarily focus on binary addition. While efforts extend the operational bit-width by minimizing the number of DNA strands and developing carry-transmission mechanisms, challenges such as the susceptibility of carrying information to attenuation and the limited expressive capacity of the binary system impose significant constraints on computational scale. This paper proposes a scalable ternary adder architecture by introducing an innovative competitive blocking (CB) circuit. The architecture employs a dual cooperative optimization strategy that significantly enhances single-bit computational capacity and incorporates a dynamic concentration adjustment (CA) to effectively broaden the computational bit-width. Consequently, a significant increase in molecular computing scale is achieved compared to previous binary adders. Biochemical experimental results indicate that the CB circuit effectively outputs the ternary full-adder bit and successfully performs 10-bit addition. Furthermore, by implementing the CA strategy, this adder can be further extended to support 17-bit addition. This research provides a novel methodological foundation for advancing DNA computing technologies and offers promising potential for scalable digital computing applications.

Figures (5)

• Figure 1: The illustration depicts the operational mechanism of the CB circuit, which encompasses three core reactions corresponding to Equations 1, 2, and 3. All reactions involving $GATE1_{ij}$ are represented by gray arrows, while those involving $GATE2$ are indicated with red arrows. It is particularly noteworthy that the reaction efficiency between $GATE1_{ij}$ and $B_{in}$ is the highest. To emphasize this significant difference in efficiency, we have intentionally employed a thicker red arrow to represent the reaction between $GATE2$ and $B_{in}$.
• Figure 2: (a) Test schemes for different toehold lengths in the $GATE1_{ij}$ structure. (b) Polyacrylamide gel electrophoresis (PAGE) results show the binding between $B_{in}$ and $GATE1_{ij}$ in the CB circuit at different concentration ratios. (c) Fluorescence detection results for SUM1 product generated by the CB circuit when the toehold lengths of $GATE1_{ij}$ are 3nt, 5nt, and 7nt, respectively. (d) Fluorescence results for SUM2 product generated by the CB circuit when the toehold lengths of $GATE1_{ij}$ are 3nt, 5nt, and 7nt. Solid lines in this figure represent the fluorescence signal of SUM2, while dashed lines indicate the leakage of SUM1 due to $B_{in}$ not fully locking $GATE1_{ij}$.
• Figure 3: (a) Truth table for the ternary adder. (b) Modular processing of the ternary adder based on its truth table. (c) Fluorescence curves for all reactions of the half adder. The results were normalized to the maximum fluorescence across all samples, and a fluorescence reading above 0.5 was considered a valid output. (d) Fluorescence curves for the SUM2 result in the 1-bit full adder. The current results were normalized to their respective maximum fluorescence values, and the output reflects the fluorescence type with the highest fluorescence. (e) Fluorescence curves for all reactions of the 1-bit full adder. All fluorescence types in the current results were normalized to their respective maximum fluorescence values; solid lines represent SUM2. Dashed lines denote SUM1 leakage, attributed to the carry information from the preceding bit not completely locking the $GATE1_{ij}$.
• Figure 4: Generation and processing of carry information strands. (a) Schematic diagram of the three-input AND gate reaction for processing the first type of scenarios. (b) Schematic diagram of the two-input AND gate reaction for processing the second type of scenarios. (c) Extraction operation for the carry information strands.
• Figure 5: (a) Schematic diagram of the catalytic reaction for the carry information strand. (b) Reaction network of a multi-bit full adder calculating 1012122101 + 2210221122. (c) The sum of two ten-bit ternary numbers. The final sum is read from the high bit to the low bit. (d) Computational performance of the ternary adder under continuous carry conditions without the CA strategy, illustrated with the example: 102102102101 + 120120120122, where the reference line represents half of the SUM2 signal, i.e., the leakage threshold. (e) Computational performance of the ternary adder under continuous carry conditions with the CA strategy, illustrated with the example: 2102102102102102101 + 0120120120120120122, where the reference line represents half of the SUM2 signal, i.e., the leakage threshold.