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Link Quality Aware Pathfinding for Chiplet Interconnects

Aaron Yen, Jooyeon Jeong, Puneet Gupta

Abstract

As chiplet-based integration advances, designers must select among short-reach die-to-die interconnect technologies with widely varying shoreline and areal bandwidth density, energy per bit, reach, and raw bit error rate (BER). Meeting stringent delivered BER targets in chiplet systems requires error-correcting codes (ECC), but incurs energy, area, and throughput overheads. We develop a flow centered around RTL synthesis power and area estimations to support pathfinding of inter-chiplet links under a stringent 10-27 delivered BER target. We synthesize a parameterized Reed-Solomon code with CRC-64 and Go-Back-N retry logic to estimate the correction overhead for different transceiver bit error rates. Results show that ECC can materially change link comparisons under common figures of merit and that CRC+ARQ can reduce the required RS strength (and decoder overhead) at moderate BERs while still meeting stringent delivered-BER targets. We present a CP-SAT-based link assignment formulation that uses these ECC-corrected metrics under reach, delivered-bandwidth, and shoreline constraints in system-level optimization.

Link Quality Aware Pathfinding for Chiplet Interconnects

Abstract

As chiplet-based integration advances, designers must select among short-reach die-to-die interconnect technologies with widely varying shoreline and areal bandwidth density, energy per bit, reach, and raw bit error rate (BER). Meeting stringent delivered BER targets in chiplet systems requires error-correcting codes (ECC), but incurs energy, area, and throughput overheads. We develop a flow centered around RTL synthesis power and area estimations to support pathfinding of inter-chiplet links under a stringent 10-27 delivered BER target. We synthesize a parameterized Reed-Solomon code with CRC-64 and Go-Back-N retry logic to estimate the correction overhead for different transceiver bit error rates. Results show that ECC can materially change link comparisons under common figures of merit and that CRC+ARQ can reduce the required RS strength (and decoder overhead) at moderate BERs while still meeting stringent delivered-BER targets. We present a CP-SAT-based link assignment formulation that uses these ECC-corrected metrics under reach, delivered-bandwidth, and shoreline constraints in system-level optimization.
Paper Structure (17 sections, 11 equations, 8 figures, 4 tables, 1 algorithm)

This paper contains 17 sections, 11 equations, 8 figures, 4 tables, 1 algorithm.

Figures (8)

  • Figure 1: Overall flow of link assignment.
  • Figure 2: FoM vs. reach (mm) for representative links. Crosses denote raw transceiver FoM, and open circles show ECC-corrected FoM using hybrid FEC+CRC+ARQ. FoM is defined as payload throughput density (Gbps/mm) divided by energy per delivered bit (pJ/bit).
  • Figure 3: Selected RS-FEC decoder energy per info bit and code rate vs input BER for a post-FEC BER target of $10^{-27}$ (ASAP7 synthesis sweep, highest-rate $K$ meeting target). Left: energy per info bit [pJ/bit]. Right: code rate ($K/N$).
  • Figure 4: RS-FEC throughput density vs. input BER (ASAP7, post-FEC BER = $10^{-27}$). X-axis: pre-FEC BER. Left: throughput density (Gbps/mm). Right: throughput density (Gbps/mm$^2$).
  • Figure 5: ECC energy and goodput vs input BER (ASAP7), comparing FEC-only and a no-drop (unbounded-retry) FEC+CRC+ARQ hybrid. Left: energy per payload bit [pJ/bit]. Right: goodput rate.
  • ...and 3 more figures