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Unifying Logical and Physical Layout Representations via Heterogeneous Graphs for Circuit Congestion Prediction

Runbang Hu, Bo Fang, Bingzhe Li, Yuede Ji

TL;DR

VeriHGN is proposed, a verification framework built on an enhanced heterogeneous graph that unifies circuit components and spatial grids into a single relational representation, enabling more faithful modeling of the interaction between logical intent and physical realization.

Abstract

As Very Large Scale Integration (VLSI) designs continue to scale in size and complexity, layout verification has become a central challenge in modern Electronic Design Automation (EDA) workflows. In practice, congestion can only be accurately identified after detailed routing, making traditional verification both time-consuming and costly. Learning-based approaches have therefore been explored to enable early-stage congestion prediction and reduce routing iterations. However, although prior methods incorporate both netlist connectivity and layout features, they often model the two in a loosely coupled manner and primarily produce numerical congestion estimates. We propose VeriHGN, a verification framework built on an enhanced heterogeneous graph that unifies circuit components and spatial grids into a single relational representation, enabling more faithful modeling of the interaction between logical intent and physical realization. Experiments on industrial benchmarks, including ISPD2015, CircuitNet-N14, and CircuitNet-N28, demonstrate consistent improvements over state-of-the-art methods in prediction accuracy and correlation metrics.

Unifying Logical and Physical Layout Representations via Heterogeneous Graphs for Circuit Congestion Prediction

TL;DR

VeriHGN is proposed, a verification framework built on an enhanced heterogeneous graph that unifies circuit components and spatial grids into a single relational representation, enabling more faithful modeling of the interaction between logical intent and physical realization.

Abstract

As Very Large Scale Integration (VLSI) designs continue to scale in size and complexity, layout verification has become a central challenge in modern Electronic Design Automation (EDA) workflows. In practice, congestion can only be accurately identified after detailed routing, making traditional verification both time-consuming and costly. Learning-based approaches have therefore been explored to enable early-stage congestion prediction and reduce routing iterations. However, although prior methods incorporate both netlist connectivity and layout features, they often model the two in a loosely coupled manner and primarily produce numerical congestion estimates. We propose VeriHGN, a verification framework built on an enhanced heterogeneous graph that unifies circuit components and spatial grids into a single relational representation, enabling more faithful modeling of the interaction between logical intent and physical realization. Experiments on industrial benchmarks, including ISPD2015, CircuitNet-N14, and CircuitNet-N28, demonstrate consistent improvements over state-of-the-art methods in prediction accuracy and correlation metrics.
Paper Structure (18 sections, 24 equations, 6 figures, 4 tables)

This paper contains 18 sections, 24 equations, 6 figures, 4 tables.

Table of Contents

  1. Introduction
  2. Background and Related Work
  3. Learning-Based Congestion Prediction
  4. Heterogeneous Graph Neural Networks
  5. Multi-Scale Spatial Modeling for Routing Congestion
  6. Methodology
  7. Congestion Prediction Graph Construction
  8. Enriched Feature Engineering
  9. Relation-Specific Message Passing
  10. Hierarchical Grid Representation Learning
  11. Congestion Prediction and Training Objective
  12. Experiment
  13. Experimental Setup
  14. Congestion Prediction Comparison
  15. Ablation Study
  16. ...and 3 more sections

Figures (6)

  • Figure 1: Example of routing congestion formation in a placement–routing workflow. (a): multiple logic blocks are placed on the layout grid with interconnecting nets. (b): global routing paths overlap and compete for limited routing resources, creating localized routing congestion. (c): accumulated routing demand is visualized as a congestion map, where colors indicate congestion levels (low to high), and red regions highlight areas where routing demand exceeds available capacity.
  • Figure 2: Overview of VeriHGN graph construction. Starting from the original circuit design ( ), we derive (i) a hierarchical grid representation ( ) capturing multi-level spatial structure, (ii) a netlist graph ( ) modeling circuit connectivity and (iii) a cell-to-grid relationship graph ( ) that encodes the spatial assignment of cells to grid locations. These components are finally integrated into a unified heterogeneous graph ( ),enabling joint structural and spatial message passing
  • Figure 3: Relation-based message passing. Messages are propagated along different relation types (cell–net, grid–net, geom–cell, and cell–grid) using relation-specific MLPs, enabling information exchange across circuit components and spatial grids.
  • Figure 4: Hierarchical grid representation learning. Grid features are aggregated from fine to coarse levels and then propagated back from coarse to fine levels, enabling multi-scale spatial information exchange.
  • Figure 5: Embedding and readout. Embeddings from different node types (cell, geom, net, and grid) are concatenated and mapped through a readout layer to produce the final congestion heatmap.
  • ...and 1 more figures