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Reducing Quantum Error Mitigation Bias Using Verifiable Benchmark Circuits

Joseph Harris, Kevin Lively, Peter Schuhmacher

Abstract

We present a simple, malleable and low-overhead approach for improving generic biased quantum error mitigation (QEM) methods, achieving up to 15% fidelity improvements over standard QEM on 100-qubit circuits with up to 2000 entangling gates. We do so by constructing verifiable benchmark circuits which mirror the application circuit's native-gate structure and thus noise profile. These circuits can be used to benchmark and mitigate the bias of the underlying error mitigation method, requiring only the application circuit and hardware native gate set. We present two methods for generating benchmark circuits; one is agnostic to the target hardware at the expense of a small overhead of single-qubit gates, while the other is specific to the IBM superconducting hardware and has no gate overhead. As a corollary, we introduce benchmarked-noise zero-noise extrapolation (bnZNE) as a simple adaptation of zero-noise extrapolation (ZNE), one of the most popular error mitigation methods. We consider as an example the bias-mitigated ZNE and bnZNE of Trotterized Hamiltonian simulations, observing that our approaches outperform standard ZNE using both small-scale classical simulations and 100-qubit utility-scale experiments on the IBM superconducting hardware. We consider the measurement of both single-site observables as well as two-site correlations along a one-dimensional qubit chain. We also provide a software package for implementing the error mitigation techniques used in this research.

Reducing Quantum Error Mitigation Bias Using Verifiable Benchmark Circuits

Abstract

We present a simple, malleable and low-overhead approach for improving generic biased quantum error mitigation (QEM) methods, achieving up to 15% fidelity improvements over standard QEM on 100-qubit circuits with up to 2000 entangling gates. We do so by constructing verifiable benchmark circuits which mirror the application circuit's native-gate structure and thus noise profile. These circuits can be used to benchmark and mitigate the bias of the underlying error mitigation method, requiring only the application circuit and hardware native gate set. We present two methods for generating benchmark circuits; one is agnostic to the target hardware at the expense of a small overhead of single-qubit gates, while the other is specific to the IBM superconducting hardware and has no gate overhead. As a corollary, we introduce benchmarked-noise zero-noise extrapolation (bnZNE) as a simple adaptation of zero-noise extrapolation (ZNE), one of the most popular error mitigation methods. We consider as an example the bias-mitigated ZNE and bnZNE of Trotterized Hamiltonian simulations, observing that our approaches outperform standard ZNE using both small-scale classical simulations and 100-qubit utility-scale experiments on the IBM superconducting hardware. We consider the measurement of both single-site observables as well as two-site correlations along a one-dimensional qubit chain. We also provide a software package for implementing the error mitigation techniques used in this research.
Paper Structure (18 sections, 32 equations, 11 figures, 1 table)

This paper contains 18 sections, 32 equations, 11 figures, 1 table.

Figures (11)

  • Figure 1: Many error mitigation methods result in a less-biased expectation value distribution with greater variance compared to the unmitigated noisy distribution. Our work is to benchmark and mitigate the remaining bias, producing a bias-mitigated ('b-mit') distribution.
  • Figure 2: Bias mitigation of zero-noise extrapolation using 10-qubit simulations of the two-dimensional kicked Ising ($H_1$) and Heisenberg ($H_2$) models with depolarizing noise. We benchmark both the bias and variance of the application error mitigation (circles) using the benchmark circuits (crosses) with $3\sigma$ errorbars, then mitigate this bias (diamonds). In all cases we see almost full elimination of the fidelity bias, validating our analytical results from section \ref{['bias-mit-subsec']}.
  • Figure 3: Measurement results of single-site $\braket{Z}$ expectation values from 100-qubit experiments using the ibm_ fez superconducting device. We propagate a one-dimensional 100-site kicked Ising chain and perform (a) ZNE, (b) bias-mitigated ZNE, (c) bnZNE, and (d) bias-mitigated bnZNE. We also use Pauli twirling, DD and TREX, see text for details. We measure single-site magnetisations $\braket{Z}$ for each qubit and plot the mean fidelity averaged over all 100 qubits with $3\sigma$ errorbars. We also plot the RMSE calculated over all sites. Circuits with 5, 10, 20 Trotter layers contained 495, 990, 1980 $\text{CZ}$ gates respectively. We see in each case that our bnZNE method outperforms standard ZNE in terms of both the mean fidelity and RMSE. For 5 and 10 Trotter layers, we see an improvement to our results via the bias mitigation.
  • Figure 4: Measurement of the two-qubit correlations $\braket{Z_xZ_{x+y}}^\text{corr}$ for a 100-site one-dimensional kicked Ising chain with 20 Trotter layers ran on the ibm_ fez superconducting device. We compare the exact values against results obtained using the ZNE, bias-mitigated ZNE, bnZNE, and bias-mitigated bnZNE error mitigation methods.
  • Figure 5: Measurement of the exponential decay rate in two-qubit correlations for the first 80 qubits in the 100-qubit chain. For each qubit $q$ we measure the exponentially decaying correlations $\braket{Z_q Z_{q+i}}^\text{corr}$ for $i=1,2,\dots,20$ using each QEM method and extract the decay rate. We observe that, whilst our bnZNE still outperforms standard ZNE, the two bias-mitigated methods offer significant improvements with b-mit bnZNE performing the best.
  • ...and 6 more figures