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ALD Oxidant as A Tuning Knob for Memory Window Expansion in Ferroelectric FETs for Vertical NAND Applications

Ranie Jeyakumar, Prasanna Venkatesan, Lance Fernandes, Salma Soliman, Priyankka Ravikumar, Taeyoung Song, Chengyang Zhang, Woohyun Hwang, Kwangyou Seo, Suhwan Lim, Wanki Kim, Daewon Ha, Shimeng Yu, Suman Datta, Asif Khan

Abstract

Dielectric inserts are widely used to expand the memory window (MW) in ferroelectric FETs (FeFETs) for vertical NAND applications, with prior efforts focused primarily on material selection and stack positioning. Here, we demonstrate that the ALD oxidant used for the Al2O3 interlayer serves as a process-level tuning knob for MW engineering. H2O-grown Al2O3 yields a significantly larger MW (7-8 V) compared to O3 (4 V) for both gate-injection (12/3) and tunnel dielectric (8/3/8) configurations. While the tunnel dielectric (8/3/8) stack maintains robust retention up to 1e4s at 125C despite the larger MW, the gate-injection (12/3) configuration exhibits pronounced retention degradation for the H2O case. The enhanced MW is attributed to higher interlayer leakage associated with H2O-based ALD. These results establish oxidant choice as a key process parameter for co-optimizing MW and retention in ferroelectric NAND technologies.

ALD Oxidant as A Tuning Knob for Memory Window Expansion in Ferroelectric FETs for Vertical NAND Applications

Abstract

Dielectric inserts are widely used to expand the memory window (MW) in ferroelectric FETs (FeFETs) for vertical NAND applications, with prior efforts focused primarily on material selection and stack positioning. Here, we demonstrate that the ALD oxidant used for the Al2O3 interlayer serves as a process-level tuning knob for MW engineering. H2O-grown Al2O3 yields a significantly larger MW (7-8 V) compared to O3 (4 V) for both gate-injection (12/3) and tunnel dielectric (8/3/8) configurations. While the tunnel dielectric (8/3/8) stack maintains robust retention up to 1e4s at 125C despite the larger MW, the gate-injection (12/3) configuration exhibits pronounced retention degradation for the H2O case. The enhanced MW is attributed to higher interlayer leakage associated with H2O-based ALD. These results establish oxidant choice as a key process parameter for co-optimizing MW and retention in ferroelectric NAND technologies.
Paper Structure (4 sections, 4 figures)

This paper contains 4 sections, 4 figures.

Table of Contents

  1. Introduction
  2. Experimental Details
  3. Results and Discussions
  4. Conclusion

Figures (4)

  • Figure 1: Schematic of the device structures with (a) 12/3 and (b) 8/3/8 gate stack is shown, (b) DC-IV characteristics of the two devices with 12/3 gate stack and 8/3/8 gate stack are shown. (c) MW as a function of V$_{WR}$ with pulse width of 100 $\mu$s for all the stacks
  • Figure 2: Retention of FEFETs with the (a) 8/3/8 stack with H$_2$o, (b) 8/3/8 ozone, (c) 12/3 H$_2$o and (d) 12/3 ozone Al2O3 layers are shown. Retention of the program and erase states is measured up to 10$^4$ s done at RT, 75 $^\circ$C, and 125 $^\circ$C.
  • Figure 3: (a) Leakage characteristics of the Al2O3 layer measured from MIM deposited through H$_2$O and ozone, C-V characteristics of the (b) 12/3 and 8/3/8 devices with both layers showing similar dielectric constant, PUND measurements in (c) 12/3 and 8/3/8 FeFETs showing higher 2P$_r$ for the device with H$_2$O Al2O3 layer
  • Figure 4: (a) Memory window (MW) at $t = 10^{4}$ s versus initial MW ($t = 0$ s) for 8/3/8 (circles) and 12/3 (triangles) FeFET stacks with H$_2$O and O$_3$ Al$_2$O$_3$ interlayers measured at 25 $^\circ$C, 75 $^\circ$C, and 125 $^\circ$C. The dashed line indicates ideal retention (0% loss). (b) Benchmark comparison of MW and retention loss with prior FeFET reports.