Extension of ACETONE C code generator for multi-core architectures

TL;DR

This paper begins an extension of ACETONE for the generation of parallel code by formally defining the processor assignment problem and surveying the state of the art on existing solutions, and introduces the implementation of the scheduling heuristic and the creation of templates implementing synchronization mechanisms.

Abstract

As the industry's interest in machine learning has grown in recent years, some solutions have emerged to safely embed them in safety-critical systems, such as the C code generator ACETONE. However, this framework is limited to generating sequential code, which cannot make most of the multi-core architectures. In this paper, we initiate an extension of ACETONE for the generation of parallel code by formally defining our processor assignment problem and surveying the state of the art on existing solutions. In the final paper, we will introduce the completed extension, including the implementation of the scheduling heuristic, the creation of templates implementing synchronization mechanisms, and an evaluation of the worst-case execution time of the framework's layers.

Figures (11)

• Figure 1: LeNet-5 neural network
• Figure 2: Modified LeNet-5 neural network
• Figure 3: Example of a DAG. In black the original graph, and in red the new node and edges used to compute a one-sink graph.
• Figure 4: Scheduling of the node 7 using ISH. A "*" means that the node is not yet scheduled, a gray background is a delay induced by the communication between cores and a red background means the node has been scheduled during the insertion step.
• Figure 5: Scheduling of the node 5 using DSH. A "*" means that the node is not yet scheduled and a gray background is a delay induced by the communication between cores.